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參數(shù)資料
| 型號： | L84225 |
| 英文描述： | L84225 100BaseTX/FX/10BaseT Physical Layer Device technical manual 4/02 |
| 中文描述： | L84225 100BaseTX/FX/10BaseT物理層設備的技術手冊，4月2日 |
| 文件頁數(shù)： | 82/118頁 |
| 文件大?。?/td> | 890K |
| 代理商： | L84225 |
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82 of 118
April, 2002
L84225 Quad 100BaseTX/FX/10BaseT Phys. Layer Device - Technical Manual
Copyright 1999-2002 by LSI Logic Corporation. All rights reserved.
4.7 FBI Controller Interface
The FBI (Five Bit Interface) controller interface has the same
characteristics of the MII except that the data path is five bits wide,
instead of 4 bits wide per the MII. The five-bit-wide data path is
automatically enabled when the 4B5B encoder is bypassed. Because of
this encoder/ decoder bypass, the FBI is used primarily for repeaters or
other applications where the PHY encoding/decoding function is not
needed. For more details about the FBI, see the Non-MII Based
Repeaters Section.
4.8 Repeater Applications
4.8.1 MII Based Repeaters
The L84225 can be used as the physical interface for MII based
repeaters by using the standard MII/RMII as the interface to the repeater
core.
For most repeaters, it is necessary to disable the internal CRS loopback.
This can be done by asserting the repeater input of the chip.
For some particular types of repeaters, it may be desirable to either
enable or disable AutoNegotiation, force Half Duplex operation, and
enable either 100 Mbps or 10 Mbps operation. All of these modes can
be configured by either asserting the appropriate hardware pins or by
setting the appropriate bits in the MI serial port Control register.
4.8.2 Clocks
Normally, transmit data sent over the MII/RMII/FBI is clocked into the
L84225 by the rising edge of the output clock TXCLK. It may be desirable
or necessary in some repeater applications to clock in transmit data from
a master clock from the repeater core. This would require that transmit
data be clocked in on the edge of an input clock. An input clock is
available for clocking in data on TXD by the rising edge on the CLKIN
pin. Notice from the timing diagrams that CLKIN generates TXCLK, and
TXD data is clocked in on TXCLK edges. This means that TXD data is
also clocked in on the CLKIN edge as well. Thus, an external clock
driving the CLKIN input can also be used as the clock for TXD.
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