參數(shù)資料
型號: L84225
英文描述: L84225 100BaseTX/FX/10BaseT Physical Layer Device technical manual 4/02
中文描述: L84225 100BaseTX/FX/10BaseT物理層設備的技術手冊,4月2日
文件頁數(shù): 16/118頁
文件大小: 890K
代理商: L84225
16 of 118
April, 2002
L84225 Quad 100BaseTX/FX/10BaseT Phys. Layer Device - Technical Manual
Copyright 1999-2002 by LSI Logic Corporation. All rights reserved.
2.2 Controller Interface
2.2.1 General
The L84225 has three interfaces to an external controller: Media
Independent Interface (MII), Reduced pin MII (RMII), and Five Bit
Interface (FBI). MII is the default interface. RMII is selected by asserting
the RMII_EN pin, a global control (all channels effected). FBI is selected,
on a per port basis, by setting the bypass encoder bit in the MI serial
port Channel Configuration register (Register 17).
2.2.2 MII - 100 Mbps
The MII is a nibble-wide packet data interface defined in IEEE 802.3. The
L84225 meets all MII requirements outlined in IEEE 802.3. The L84225
can directly connect, without external logic, to any Ethernet controller or
other device that also complies with the IEEE 802.3 MII specification.
The MII frame format is shown in
Figure 3
.
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