參數(shù)資料
型號(hào): L84225
英文描述: L84225 100BaseTX/FX/10BaseT Physical Layer Device technical manual 4/02
中文描述: L84225 100BaseTX/FX/10BaseT物理層設(shè)備的技術(shù)手冊(cè),4月2日
文件頁(yè)數(shù): 32/118頁(yè)
文件大小: 890K
代理商: L84225
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32 of 118
April, 2002
L84225 Quad 100BaseTX/FX/10BaseT Phys. Layer Device - Technical Manual
Copyright 1999-2002 by LSI Logic Corporation. All rights reserved.
Figure 5
TP Input Voltage Template - 10 Mbps
In the unsquelch state, the receive threshold level is reduced by
approximately 30% for noise immunity reasons and is called the
unsquelch level. When the receiver is in the unsquelch state the input
signal is considered valid.
The device stays in the unsquelch state until loss of data is detected.
Loss of data is detected if no alternating polarity unsquelch transitions
are detected during any 10 us interval. When the loss of data is detected,
the receive squelch level is re-established.
2.9.4 Squelch - 10 Mbps
The TP squelch algorithm for 10 Mbps mode is identical to the 100 Mbps
mode, except:
The 10 Mbps squelch algorithm is not used for link integrity, but to
sense the beginning of a packet.
a. Short Bit
585 mV sin (
π
t/PW)
0
PW
585 mV
3.1 V
Slope 0.5 V/ns
585 mV
3.1 V
b. Long Bit
585 mV sin [2
π
(t
PW2)/PW]
585 mV sin (
π
t/PW)
Slope 0.5 V/ns
0
PW/4
3PW/4
PW
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