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參數(shù)資料
| 型號： | L84225 |
| 英文描述： | L84225 100BaseTX/FX/10BaseT Physical Layer Device technical manual 4/02 |
| 中文描述： | L84225 100BaseTX/FX/10BaseT物理層設(shè)備的技術(shù)手冊，4月2日 |
| 文件頁數(shù)： | 83/118頁 |
| 文件大小： | 890K |
| 代理商： | L84225 |
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Application Information
Copyright 1999-2002 by LSI Logic Corporation. All rights reserved.
83 of 118
April, 2002
4.9 Serial Port
4.9.1 General
The L84225 has an MI serial port to set all of the devices' configuration
inputs and read out the status outputs. Any external device that has an
IEEE 802.3 compliant MI interface can connect directly to the L84225
without any glue logic, as shown in
Figure 11
and
Figure 12
.
As described earlier, the MI serial port consists of five lines: MDC, MDIO,
and PHYAD[4:2]. However, only 2 lines, MDC and MDIO, are needed to
shift data in and out.
PHYAD[4:2] define the three most significant bits of the PHY address, as
described in
Section 4.9.3, “Serial Port Addressing,” page 83
.
4.9.2 Polling vs. Interrupt
The status output bits can be monitored by either polling the serial port
or with the interrupt output.
If polling is used, the registers can be read at regular intervals and the
status bits can be checked against their previous values to determine any
changes. To make polling simpler, all the registers can be accessed in a
single read or write cycle by setting the register address bits REGAD[4:0]
to 11111 and adding enough clocks to read out all the bits, provided the
multiple register access feature has been enabled.
4.9.3 Serial Port Addressing
The device address for the MI serial port is selected by connecting the
PHYAD[4:2] pins to the desired value. The PHYAD[1:0] addresses are
internally hardwired for each channel as shown in both
Table 6
and
Table 8
.
4.10 Unmanaged Port Configuration
The L84225 has configuration inputs which can “over-ride” the default
configuration state obtained on POWER-UP or RESET of the device.
Use of these pins ANEG, SPEED_[3:0], and DPLX_[3:0] allow selection
of Global AutoNegotiation, Individual Port Speed (10/100), and Individual
Port Duplex (Full/Half), by properly strapping these pins to VDD or VSS
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