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參數(shù)資料
| 型號： | L84225 |
| 英文描述： | L84225 100BaseTX/FX/10BaseT Physical Layer Device technical manual 4/02 |
| 中文描述： | L84225 100BaseTX/FX/10BaseT物理層設(shè)備的技術(shù)手冊，4月2日 |
| 文件頁數(shù)： | 37/118頁 |
| 文件大小： | 890K |
| 代理商： | L84225 |
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Functional Description
Copyright 1999-2002 by LSI Logic Corporation. All rights reserved.
37 of 118
April, 2002
2.11.4 Collision Indication
Collision can be programmed to appear on the LED2 pin by appropriately
setting the LED definition bits in the MI serial port Global Configuration
register.
Section 2.23, “LED Drivers,” page 48
, describes the
programmable LED definition bit settings. When the LED2 pin is
programmed to be a collision detect output, the pin is asserted low for
100 ms every time a collision occurs.
2.12 Start of Packet
2.12.1 100 Mbps
Start of packet for 100 Mbps mode is indicated by a unique Start of
Stream Delimiter (SSD). The SSD pattern consists of the two /J/K/ 5B
symbols inserted at the beginning of the packet in place of the first two
preamble symbols, as defined in IEEE 802.3 Clause 24 and shown in
Table 3
and
Figure 2
.
The transmit SSD is generated by the 4B5B encoder and the /J/K/
symbols are inserted by the 4B5B encoder at the beginning of the
transmit data packet in place of the first two 5B symbols of the preamble,
as shown in
Figure 2
.
The receive pattern is detected by the 4B5B decoder by examining
groups of 10 consecutive code bits (two 5B words) from the descrambler.
Between packets, the receiver will be detecting the idle pattern, which is
5B /I/ symbols. While in the idle state, CRS and RXDV are deasserted.
If the receiver is in the idle state and 10 consecutive code bits from the
receiver consist of the /J/K/ symbols, the start of packet is detected, data
reception is begun, CRS and RXDV are asserted, and /5/5/ symbols are
substituted in place of the /J/K/ symbols.
If the receiver is in the idle state and 10 consecutive code bits from the
receiver consist of a pattern that is neither /I/ I/ nor /J/K/ symbols but
contains at least 2 non-contiguous 0's, then activity is detected but the
start of packet is considered to be faulty and a False Carrier Indication
(also referred to as bad SSD) is signaled to the controller interface. When
False Carrier is detected CRS is asserted, RXDV remains deasserted,
RXD[3:0]=1110 while RXER is asserted, and the bad SSD bit is set in
the MI serial port Channel Status Output register. Once a False Carrier
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