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參數(shù)資料
| 型號： | KAB04D100M-TLGP |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | Multi-Chip Package MEMORY |
| 中文描述： | 多芯片封裝存儲器 |
| 文件頁數(shù)： | 34/72頁 |
| 文件大?。?/td> | 1378K |
| 代理商： | KAB04D100M-TLGP |
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KAB0xD100M - TxGP
Revision 1.11
August 2003
- 34 -
MCP MEMORY
SEC Only
Figure 17. Block Erase Operation
BLOCK ERASE
The Erase operation is done on a block(16K Bytes) basis. Block Erase is executed by entering Erase Setup command(60h) and 2
cycle block addresses and Erase Confirm command(D0h). Only address A14 to A23 is valid while A9 to A13 is ignored. This two-
step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external
noise condition. At the rising edge of WE after erase confirm command input, internal write controller handles erase and erase-ver-
ification. When the erase operation is completed, the Write Status Bit(I/O 0) may be checked.
Figure 6 details the sequence.
60h
Block Add. : A
9
~ A
23
DQ
x
R/B
F
Address Input(2Cycle)
DQ
0
Pass
D0h
70h
Fail
t
BERS
READ STATUS
The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether
the program or erase operation is completed successfully. After writing 70h command to command register, a read cycle takes out
the content of the Status Register to the I/O pins on the falling edge of CE
F
or RE. This two line control allows the system to poll the
progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE
F
does not need to be
toggled for updated status. Refer to table 16 for specific Status Register definitions. The command register remains in Status Read
mode until further commands are issued to it. Therefore, if the status register is read during a random read cycle, a read com-
mand(00h or 50h) should be given before sequential page read cycle.
Table 16. Read Status Register Definition
DQ #
Status
Definition
DQ
0
Program / Erase
"0" : Successful Program / Erase
"1" : Error in Program / Erase
DQ
1
Reserved for Future
Use
"0"
DQ
2
"0"
DQ
3
"0"
DQ
4
"0"
DQ
5
"0"
DQ
6
Device Operation
"0" : Busy "1" : Ready
DQ
7
Write Protect
"0" : Protected "1" : Not Protected
DQ
8~15
Not use
Don’t care
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| KAB04D100M-TNGP | Multi-Chip Package MEMORY |
| KAB01D100M | Tantalum Conformal-Coated Capacitor; Capacitance: 22uF; Voltage: 10V; Packaging: Tape & Reel |
| KAB02D100M-TLGP | Tantalum Conformal-Coated Capacitor; Capacitance: 22uF; Voltage: 10V; Packaging: Tape & Reel |
| KAB01D100M-TNGP | CONNECTOR ACCESSORY |
| KAB02D100M-TNGP | CONNECTOR ACCESSORY |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KAB04D100M-TNGP | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:Multi-Chip Package MEMORY |
| KAB-1 | 功能描述:保險絲 TRON RECTIFIER FUSE RoHS:否 制造商:Littelfuse 產(chǎn)品:Surface Mount Fuses 電流額定值:0.5 A 電壓額定值:600 V 保險絲類型:Fast Acting 保險絲大小/組:Nano 尺寸:12.1 mm L x 4.5 mm W 安裝風(fēng)格: 端接類型:SMD/SMT 系列:485 |
| KAB-1/2 | 制造商:COOPER BUSSMANN 功能描述:TRON RECTIFIER FUSE |
| KAB-10 | 功能描述:保險絲 10A RoHS:否 制造商:Littelfuse 產(chǎn)品:Surface Mount Fuses 電流額定值:0.5 A 電壓額定值:600 V 保險絲類型:Fast Acting 保險絲大小/組:Nano 尺寸:12.1 mm L x 4.5 mm W 安裝風(fēng)格: 端接類型:SMD/SMT 系列:485 |
| KAB-100 | 制造商:Cooper Bussmann 功能描述: |
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