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KAB0xD100M - TxGP
Revision 1.11
August 2003
- 33 -
MCP MEMORY
SEC Only
PAGE PROGRAM
The device is programmed basically on a page basis, but it allows multiple partial page program of one word or consecutive words up
to 264, in a single page program cycle. The number of consecutive partial page program operation within the same page without
intervening erase operation should not exceed 2 for main array and 3 for spare array. The addressing may be done in any random
order in a block. Page program cycle consists of a serial data loading(up to 264 words of data) into the page register, and program of
loaded data into the appropriate cell. Serial data loading can start in 2nd half array by moving pointer. About the pointer operation,
please refer to the attached technical notes. Serial data loading is executed by entering the Serial Data Input command(80h) and
three cycle address input and then serial data loading. The bytes except those to be programmed need not to be loaded. The Page
Program confirm command(10h) initiates the programming process. Writing 10h alone without previously entering 80h will not initiate
program process. The internal write controller automatically executes the algorithms and timings necessary for program and verifica-
tion, thereby freeing the CPU for other tasks. Once the program process starts, the Read Status Register command may be entered,
with RE and CE low, to read the status register. The CPU can detect the completion of a program cycle by monitoring the R/B out-
put, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset command are valid while programming
is in progress. When the Page Program is completed, the Write Status Bit(I/O 0) may be checked(Figure 16). The internal write veri-
fication detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read Status
command mode until another valid command is written to the command register.
Figure 16 details the sequence.
Figure 16. Program & Read Status Operation
80h
DQ
x
R/B
F
Address & Data Input
DQ
0
Pass
10h
70h
Fail
t
PROG
Figure 15. Read2 Operation
50h
A
0
~ A
2
& A
9
~ A
23
Data Output(Sequential)
Spare Field
CE
CLE
ALE
R/B
F
WE
Data Field
Spare Field
Start Add.(3Cycle)
(A
3
~ A
7
:
"L")
DQ
x
RE
t
R