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參數(shù)資料
| 型號： | KAB01D100M-TNGP |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | CONNECTOR ACCESSORY |
| 中文描述： | 連接器附件 |
| 文件頁數(shù)： | 68/72頁 |
| 文件大?。?/td> | 1378K |
| 代理商： | KAB01D100M-TNGP |
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KAB0xD100M - TxGP
Revision 1.11
August 2003
- 68 -
MCP MEMORY
SEC Only
TIMING WAVEFORM OF WRITE CYCLE(3)
(UB, LB Controlled
,
ZZ=V
IH
)
(WRITE CYCLE)
1. A wri
t
e occurs during the overlap(t
WP
) of low CS
U
and low WE. A write begins when CS
U
goes low and WE goes low with asserting
UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest tran-
sition when CS
U
goes high and WE goes high. The
t
WP
is measured from the beginning of write to the end of write.
2.
t
CW
is measured from the CS
U
going low to the end of write.
3. t
AS
is measured from the address valid to the beginning of write.
4.
t
WR
is measured from the end of write to the address change.
t
WR
applied in case a write ends as CS
U
or WE going high.
Address
Data Valid
UB, LB
WE
Data in
Data out
High-Z
High-Z
t
WC
t
CW(2)
t
BW
t
WP(1)
t
DH
t
DW
t
WR(4)
t
AW
t
AS(3)
CS
U
TIMING WAVEFORM OF DEEP POWER DOWN MODE
(DEEP POWER DOWN MODE)
1. When you toggle ZZ pin low, the device gets into the Deep Power Down mode after 0.5
μ
s suspend period.
2. To return to normal operation, the device needs Wake Up period.
3. Wake Up sequence is just the same as Power up sequences.
ZZ
MODE
Deep Power Down Mode
Normal Operation
0.5
μ
s
200
μ
s
≈
Normal Operation
Read Operation Twice or Stay High during 300
μ
s
Suspend
Wake up
CS
U
≈
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相關(guān)代理商/技術(shù)參數(shù) |
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| KAB02D100M-TLGP | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:Multi-Chip Package MEMORY |
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| KAB03D100M-TLGP | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:Multi-Chip Package MEMORY |
| KAB03D100M-TNGP | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:Multi-Chip Package MEMORY |
| KAB04D100M-TLGP | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:Multi-Chip Package MEMORY |
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