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KAB0xD100M - TxGP
Revision 1.11
August 2003
- 18 -
MCP MEMORY
SEC Only
Figure 4. Autoselect Operation
WE
555H/
AAAH
2AAH/
555H
555H/
AAAH
AAH
55H
90H
00H/
00H
01H/
02H
ECH
Manufacturer
Code
Device Code
A21
~
A0(x16)/*
A21
~
A-1(x8)
DQ15
~
DQ0
F0H
Return to
Read Mode
22or
22E2H
NOTE:
The 3rd Cycle and 4th Cycle address must include the same bank address. Please refer to Table 6 for device code.
Write (Program/Erase) Mode
The NOR Flash memory executes its program/erase operations by writing commands into the command register. In order to write the
commands to the register, CE
R
and WE must be low and OE must be high. Addresses are latched on the falling edge of CE
R
or WE
(whichever occurs last) and the data are latched on the rising edge of CE
R
or WE (whichever occurs first). The device uses standard
microprocessor write timing.
Program
The NOR Flash memory can be programmed in units of a word or a byte. Programming is writing 0's into the memory array by exe-
cuting the Internal Program Routine. In order to perform the Internal Program Routine, a four-cycle command sequence is neces-
sary. The first two cycles are unlock cycles. The third cycle is assigned for the program setup command. In the last cycle, the address
of the memory location and the data to be programmed at that location are written. The device automatically generates adequate pro-
gram pulses and verifies the programmed cell margin by the Internal Program Routine. During the execution of the Routine, the sys-
tem is not required to provide further controls or timings.
During the Internal Program Routine, commands written to the device will be ignored. Note that a hardware reset during a program
operation will cause data corruption at the corresponding location.
(KAB02C100 / KAB01C100)
Figure 5. Program Command Sequence
WE
555H/
AAAH
2AAH/
555H
555H/
AAAH
AAH
55H
A0H
Program
Address
Program
Data
Program
Start
DQ15-DQ0
R/B
R
A21
~
A0(x16)/
A21
~
A-1(x8)