
KAB0xD100M - TxGP
Revision 1.11
August 2003
- 45 -
MCP MEMORY
SEC Only
CAPACITANCE
(T
A
= 25
°
C, V
CC
= 2.9V, f = 1.0MHz)
NOTE:
Capacitance is periodically sampled and not 100% tested.
Item
Symbol
Test Condition
Min
Max
Unit
Input Capacitance
C
IN
V
IN
=0V
-
28
pF
Input/Output Capacitance
C
IO
V
IO
=0V
-
30
pF
VALID BLOCK OF NAND FLASH MEMORY
NOTE:
1. The NAND
Flash memory
may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of
valid blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits
.
Do not try to access these invalid blocks for program and erase.
Refer to the attached technical notes for a appropriate management of invalid blocks.
2. The 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block, does not require Error Correction.
Parameter
Symbol
Min
Typ.
Max
Unit
Valid Block Number
N
VB
1004
-
1024
Blocks
ZZ=V
IL
CS
=V
IH
ZZ=V
IH
ZZ=V
IL
CS
U
=V
IL
, UB or/and LB=V
IL
ZZ=V
IH
CS
U
=V
IH
, ZZ=V
IH
Standby Mode State Machines(U
t
RAM)
Read Operation Twice
Power On
Initial State
(Wait 200
μ
s)
Active
Standby
Mode
Deep Power
Down Mode
Standby Mode Characteristic(U
t
RAM)
Power Mode
Memory Cell Data
Standby Current(
μ
A)
Wait Time(
μ
s)
Standby
Valid
100
0
Deep Power Down
Invaild
10
200
CS
U
=V
IH
AC TEST CONDITION
NOTE:
AC test inputs are driven at Vcc
R
, Vcc
F
or Vcc
U
for a logic "1" and 0V for a logic "0". Input timing begins, and output timing ends,
at Vcc
R
/2, Vcc
F
/2 or VccQ
U
/2. Input rise and fall times (10% - 90%)<5ns. Worst case speed condition are when Vcc
R
= Vcc
R
min,
Vcc
F
= Vcc
F
min or VccQ
U
= VccQ
U
min.
Parameter
Value
Input Pulse Levels
0V to Vcc
Input Rise and Fall Times
5ns
Input and Output Timing Levels
Vcc/2 or VccQ
U
/2
C
L
= 30pF
Output Load
0V
Vcc
Vcc/2
Vcc/2 or VccQ
U
/2
Input Pulse and Test Point
Input & Output
Test Point
Output Load
*
C
L
= 30pF including Scope
and Jig Capacitance
C
L
Device