參數(shù)資料
型號(hào): K4N26323AE-GC20
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 128Mbit GDDR2 SDRAM
中文描述: 128Mbit GDDR2 SDRAM的
文件頁數(shù): 35/52頁
文件大?。?/td> 826K
代理商: K4N26323AE-GC20
- 35 -
Rev. 1.7 (Jan. 2003)
128M GDDR2 SDRAM
K4N26323AE-GC
AC CHARACTERISTICS
1. The cycle to cycle jitter and 2~6 cycle short term jitter.
Parameter
Symbol
-20 (GF1000)
Min
2.0
-
-
0.45
0.45
-0.35
-0.225
0.85
0.35
0.45
0.45
0.5
0.5
-22 (GF900)
Min
-
2.22
-
0.45
0.45
-0.45
-0.25
0.88
0.38
0.45
0.45
0.55
0.55
-25 (GF800)
Min
-
-
2.5
0.45
0.45
-0.45
-0.28
0.9
0.4
0.45
0.45
0.6
0.6
Unit
Max
4.0
-
-
0.55
0.55
0.35
0.225
1.15
0.65
0.55
0.55
-
-
Max
-
4.0
-
0.55
0.55
0.45
0.25
1.12
0.62
0.55
0.55
-
-
Max
-
-
4.0
0.55
0.55
0.45
0.28
1.1
0.6
0.55
0.55
-
-
CK cycle time
CL=7
CL=6
CL=5
tCK
ns
ns
ns
tCK
tCK
ns
ns
tCK
tCK
tCK
tCK
ns
ns
CK high width
CK low width
DQS out access time from CK
Data strobe edge to Dout edge
Read preamble
Read postamble
DQS in/out high level
DQS in/out low level
Address and Control input setup
Address and Control input hold
Write command to first DQS
latching transition
Write preamble setup time
Write postamble
Write preamble
DQ_in and DM setup time to DQS
DQ_in and DM hold time to DQS
Clock half period
Data output hold time from DQS
Jitter over 1-6 clock cycles of CK
Cycle to Cycle duty cycle error
Rise and fall times of CK
tCH
tCL
tDQSCK
tDQSQ
tRPRE
tRPST
tDQSH
tDQSL
tIS
tIH
tDQSS
WL - 0.15
WL + 0.15
WL - 0.15
WL + 0.15
WL - 0.15
WL + 0.15
tCK
tWPRES
tWPST
tWPRE
tDS
tDH
tHP
tQH
tJ *1
tDC,ERR
tR, tF
0
-
0
-
0
-
ps
tCK
tCK
ns
ns
ns
ns
ps
ps
ps
0.4
0.35
0.25
0.25
0.6
-
-
-
-
-
50
50
400
0.4
0.35
0.27
0.27
0.6
-
-
-
-
-
55
55
450
0.4
0.35
0.3
0.3
0.6
-
-
-
-
-
65
65
500
tCL/H min
tHP-0.225
-
-
-
tCL/H min
tHP-0.25
-
-
-
tCL/H min
tHP-0.28
-
-
-
Simplified Timing @ BL=4, CL=7, AL=0
0
1
CMD
Post CAS
READ A
NOP
NOP
DQ’s
CK, CK
2
7
8
9
10
11
DOUT A
0
DOUT A1
DOUT A2
DOUT A3
DQS
DIN A0
DIN A1
DIN A2
DIN A3
RL = 7
NOP
NOP
NOP
6
WDQS
NOP
NOP
NOP
Post CAS
Write A
WL = 1
12
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