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參數(shù)資料
| 型號： | K4N26323AE-GC20 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 128Mbit GDDR2 SDRAM |
| 中文描述： | 128Mbit GDDR2 SDRAM的 |
| 文件頁數(shù)： | 30/52頁 |
| 文件大?。?/td> | 826K |
| 代理商： | K4N26323AE-GC20 |
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- 30 -
Rev. 1.7 (Jan. 2003)
128M GDDR2 SDRAM
K4N26323AE-GC
4. Command Truth Table.
(V=Valid, X=Don’t Care, H=Logic High, L=Logic Low)
Function
CKE
CS
RAS
CAS
WE
DM
BA0/BA1
A11 - A9
A8
A7 - A0
Notes
Previous
Cycle
Current
Cycle
Mode Register Set
H
X
L
L
L
L
X
BA0 = 0 and MRS OP Code
1
Extended Mode Register Set
H
X
L
L
L
L
X
BA0 = 1 and EMRS OP Code
1
Auto (CBR) Refresh
H
H
L
L
L
H
X
X
X
X
X
1
Entry Self Refresh
H
L
L
L
L
H
X
X
X
X
X
1
Exit Self Refresh
L
H
H
X
X
X
X
X
X
X
X
1
L
H
L
H
H
H
X
X
X
X
X
Single Bank Precharge
H
X
L
L
H
L
X
BA
X
L
X
1,2
Precharge all Banks
H
X
L
L
H
L
X
X
X
H
X
1
Bank Activate
H
X
L
L
H
H
X
BA
Row Address
1,2
Write
H
X
L
H
L
L
X
BA
X
L
Column
1,2,3,
Write with Auto Precharge
H
X
L
H
L
L
X
BA
X
H
Column
1,2,3,
Read
H
X
L
H
L
H
X
BA
X
L
Column
1,2,3
Read with Auto-Precharge
H
X
L
H
L
H
X
BA
X
H
Column
1,2,3
DM
H
X
X
X
X
X
DM
X
X
X
X
6
No Operation
H
X
L
H
H
H
X
X
X
X
X
1
H
X
H
X
X
X
X
X
X
X
X
1
Power Down Mode Entry
H
L
H
X
X
X
X
X
X
X
X
1,4,5
H
L
L
H
H
H
X
X
X
X
X
Power Down Mode Exit
L
H
H
X
X
X
X
X
X
X
X
1,4,5
L
H
L
H
H
H
X
X
X
X
X
1. All of the GDDR2 SDRAM operations are defined by states of CS, WE, RAS, and CAS at the positive rising edge of the clock.
2. Bank Select (BA0,1), determine which bank is to be operated upon.
3. Burst read or write cycle may not be terminated.
4. The Power Down Mode does not perform any refresh operations, therefore the device can’t remain in this mode longer than the Refresh period
(t
REF
) of the device. Four clock delay is required for mode entry and exit.
5. If CS is low, then when CKE returns high, no command is registered into the chip for one clock cycle.
6. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).
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