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參數(shù)資料
| 型號： | K4N26323AE-GC20 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 128Mbit GDDR2 SDRAM |
| 中文描述： | 128Mbit GDDR2 SDRAM的 |
| 文件頁數(shù)： | 31/52頁 |
| 文件大小： | 826K |
| 代理商： | K4N26323AE-GC20 |
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- 31 -
Rev. 1.7 (Jan. 2003)
128M GDDR2 SDRAM
K4N26323AE-GC
5. Clock Enable (CKE) Truth Table
Current State
CKE
Command
Action
Notes
Previous
Cycle
Current
Cycle
CS
RAS
CAS
WE
BA1, BA0,
A11 - A0
Self Refresh
H
X
X
X
X
X
X
INVALID
1
L
H
H
X
X
X
X
Exit Self Refresh with Device Deselect
2
L
H
L
H
H
H
X
Exit Self Refresh with No Operation
2
L
H
L
Command
Address
ILLEGAL
2
L
L
X
X
X
X
X
Maintain Self Refresh
Power Down
H
X
X
X
X
X
X
INVALID
1
L
H
H
X
X
X
X
Power Down mode exit, all banks idle
2
L
H
L
H
H
H
X
Exit Power Down mode with No Operation
2
L
H
L
Command
Address
ILLEGAL
2
L
L
X
X
X
X
X
Maintain Power Down Mode
All Banks Idle
H
H
H
X
X
X
Device Deselect
3
H
H
L
Command
Address
Refer to the Current State Truth Table
3
H
L
H
X
X
X
Power Down
H
L
L
Command except self-
refresh command
X
ILLEGAL
H
L
L
L
L
H
X
Entry Self Refresh
4
Any State other
than listed
above
H
H
X
X
X
X
X
Refer to operations in the Current State
Truth Table
H
L
X
X
X
X
X
Power Down
5
L
H
X
X
X
X
X
Power Down
L
L
X
X
X
X
X
Power Down
1. For the given Current State CKE must be low in the previous cycle.
2. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. The minimum setup time for CKE (t
CES
) must be
satisfied before any command other than self refresh exit.
3. The inputs (BA1, BA0, A11 - A0) depend on the command that is issued. See the Current State Truth Table for more information.
4. The Auto Refresh, Self Refresh Mode, and the Mode Register Set modes can only be entered from the all banks idle state.
5. Must be a legal command as defined in the Current State Truth Table.
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