參數(shù)資料
型號: K4N26323AE-GC20
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 128Mbit GDDR2 SDRAM
中文描述: 128Mbit GDDR2 SDRAM的
文件頁數(shù): 33/52頁
文件大?。?/td> 826K
代理商: K4N26323AE-GC20
- 33 -
Rev. 1.7 (Jan. 2003)
128M GDDR2 SDRAM
K4N26323AE-GC
AC INPUT OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to V
SS
=0V, V
DD
=2.5V
±
0.1V, V
DDQ
=1.8V
±
0.1V, T
j
=0 to 100
°
C)
Parameter
Symbol
Min
Typ
Max
Unit
Note
Input High (Logic 1) Voltage; DQ
V
IH
V
REF
+0.25
-
-
V
1
Input Low (Logic 0) Voltage; DQ
V
IL
-
-
V
REF
-0.25
V
2
Clock Input Differential Voltage ; CK and CK
V
ID
0.5
-
V
DDQ
+0.6
V
3
Clock Input Crossing Point Voltage ; CK and CK
V
IX
0.5*V
DDQ
-0.2
-
0.5*V
DDQ
+0.2
V
4
1. V
IH
(Max) = 4.2V. The overshoot voltage duration is < 3ns at VDD.
V
IH
level should be met at the pin of DRAM when ODT=ON.
2. V
IL
(Min) = -1.5V. The undershoot voltage duration is < 3ns at VSS.
V
IL
level should be met at the pin of DRAM when ODT=ON.
3. V
ID
is the magnitude of the difference between the input level on CK and the input level on CK
4. The value of V
IX
is expected to equal 0.5*V
DDQ
of the transmitting device and must track variations in the DC level of the same
Note :
DC CHARACTERISTICS
Recommended operating conditions Unless Otherwise Noted, T
j
=0 to 100
°
C)
Note :
1. Measured with outputs open & On-Die termination off.
2. Refresh period is 16ms.
Parameter
Symbol
Test Condition
Version
Unit
Note
-20
-22
-25
Operating Current
(One Bank Active)
I
CC1
Burst Lenth=4
t
RC
t
RC
(min)
I
OL
=0mA,
t
CC
=
t
CC
(min)
590
540
500
mA
1
Precharge Standby Current
in Power-down mode
I
CC2
P
CKE
V
IL
(max),
t
CC
=
t
CC
(min)
110
100
95
mA
Precharge Standby Current
in Non Power-down mode
I
CC2
N
CKE
V
IH
(min), CS
V
IH
(min),
t
CC
=
t
CC
(min)
230
210
190
mA
Active Standby Current
power-down mode
I
CC3
P
CKE
V
IL
(max),
t
CC
=
t
CC
(min)
110
100
95
mA
Active Standby Current in
in Non Power-down mode
I
CC3
N
CKE
VIH(min), CS
VIH(min),
t
CC
=
t
CC
(min)
510
470
430
mA
Operating Current
( Burst Mode)
I
CC4
I
OL
=0mA ,
t
CC
=
t
CC
(min),
Page Burst, All Banks activated.
1200
1100
990
mA
Refresh Current
I
CC5
t
RC
t
RFC
370
350
330
mA
2
Self Refresh Current
I
CC6
CKE
0.2V
7
mA
Operating Current
(4Bank interleaving)
I
CC7
Burst Lenth=4
t
RC
t
RC
(min)
I
OL
=0mA,
t
CC
=
t
CC
(min)
1400
1300
1180
mA
Controller
DRAM
VDDQ
VSSQ
ODT of DRAM
Input level should be measured
at this point
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