參數(shù)資料
型號: K4N26323AE-GC20
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 128Mbit GDDR2 SDRAM
中文描述: 128Mbit GDDR2 SDRAM的
文件頁數(shù): 29/52頁
文件大?。?/td> 826K
代理商: K4N26323AE-GC20
- 29 -
Rev. 1.7 (Jan. 2003)
128M GDDR2 SDRAM
K4N26323AE-GC
.
The On-die Termination for external two bank system with self-calibration code (A3, A2 = 0, 1)
The external resistor (Rref) is equal to 2X the number of shared DRAM’s on one channel X target termination value of DQ
channel. The following figure is represented the typical two bank system having on-die termination. 4 DRAM’s share one
channel for CMD and ADD pins and 2 DRAM’s share one channel for DQ’s and CLK pins. The external resistor (Rref) is 4
times of target termination value on channel. The On-die Termination value of CK, /CK, 32 DQ’s, 4 DM’s, 4 /DQS’s and
4DQS pins on channel is half value of the external resistor (Rref).
Self-refresh and power down mode in two bank system should be issued for all DRAM’s at the same time to keep suit-
able On-die termination condition on channel.
VSSQ
VSSQ
VSSQ
VSSQ
1. With these case, the system couldn’t have suitable Rterm.
Because the On-Die termination value on channel is two times than the target value.
Mode
Pin
DRAM
Remarks
M1
M2
M1
M2
Self_refresh
Self_refresh
All
OFF
OFF
Self_refresh
Other States
All
Illegal
Power down
Power down
CK,/CK
ON
ON
Other pins
OFF
OFF
Power down
Other States
Illegal
All Banks idle
Active
CK, /CK, ADD’s, CMD
ON
ON
DQ’s, DQS’s, /DQS’s, DM’s
ON
ON
Read
A10=1
CK, /CK, ADD’s, CMD
ON
ON
DQ’s, DQS’s, /DQS’s, DM’s
ON
OFF
A10=0
CK, /CK, ADD’s, CMD
ON
ON
DQ’s, DQS’s, /DQS’s, DM’s
ON
ON
Active
Read
A10=1
CK, /CK, ADD’s, CMD
ON
ON
DQ’s, DQS’s, /DQS’s, DM’s
ON
OFF
A10=0
CK, /CK, ADD’s, CMD
ON
ON
DQ’s, DQS’s, /DQS’s, DM’s
ON
ON
*1
*1
Block Diagram of 2 Banks System
CK, /CK
ADD
/WE, /CS
DM’s, DQ’s,
DQS’s, /DQS’s
CK, /CK
DM’s, DQ’s,
DQS’s, /DQS’s
CK, /CK
DM’s, DQ’s,
DQS’s, /DQS’s
CK, /CK
/WE, /CS
DQS’s, /DQS’s
C
CK, /CK
ADD
/RAS, /CAS, /WE, /CS
DM’s, DQ’s,
DQS’s, /DQS’s
CK, /CK
DM’s, DQ’s,
DQS’s, /DQS’s
CK, /CK
/CS
/RAS, /CAS, /WE, /CS
DM’s, DQ’s,
DQS’s, /DQS’s
CK, /CK
DM’s, DQ’s,
DQS’s, /DQS’s
CK, /CK
ADD
/WE, /CS
DM’s, DQ’s,
DQS’s, /DQS’s
CK, /CK
DM’s, DQ’s,
DQS’s, /DQS’s
CK, /CK
DQS’s, /DQS’s
CK, /CK
DQS’s, /DQS’s
Front Side DRAM’s
Back Side DRAM’s
ZQ
Rref = 4 X Rterm
ZQ
4 X Rterm
ZQ
4 X Rterm
ZQ
4 X Rterm
ZQ
4 X Rterm
ZQ
4 X Rterm
ZQ
4 X Rterm
ZQ
4 X Rterm
ADD
/WE, /CS
ADD
/WE, /CS
ADD
/WE, /CS
ADD
/RAS, /CAS,
DM’s, DQ’s,
ADD
ADD
/RAS, /CAS,
DM’s, DQ’s,
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