參數(shù)資料
型號(hào)： HYB18L128160BF
廠商： QIMONDA
英文描述： DRAMs for Mobile Applications 128-Mbit Mobile-RAM
中文描述： 針對(duì)移動(dòng)應(yīng)用的DRAM 128 - Mbit的移動(dòng)RAM
文件頁(yè)數(shù)： 14/55頁(yè)
文件大?。?/td> 1399K
代理商： HYB18L128160BF
Data Sheet
14
Rev. 1.71, 2007-01
05282004-NZNK-8T0D
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional DescriptionCommands
2.4
Commands
Address (A0 - A11, BA0, BA1), write data (DQ0 - DQ15) and command inputs (CKE, CS, RAS, CAS, WE, DQM)
are all registered on the positive edge of CLK.
Figure 5
shows the basic timing parameters, which apply to all
commands and operations.
Table 7
Command
NOP DESELECT
NO OPERATION
ACT
ACTIVE (Select bank and row)
RD
READ (Select bank and column and start read burst)
WR
WRITE (Select bank and column and start write burst) L
BST
BURST TERMINATE or
DEEP POWER DOWN
PRE
PRECHARGE (Deactivate row in bank or banks)
ARF
AUTO REFRESH or
SELF REFRESH (enter self refresh mode)
MRS MODE REGISTER SET
–
Data Write / Output Enable
–
Write Mask / Output Disable (High-Z)
Command Overview
CS RAS CAS WE DQM
H
X
X
L
H
H
L
L
H
L
H
L
H
L
L
H
H
Address
X
X
Bank / Row
Bank / Col
Bank / Col
X
Notes
1)
X
H
H
H
L
L
X
X
X
L/H
L/H
X
1) DESELECT and NOP are functionally interchangeable.
2) BA0, BA1 provide bank address, and A0 - A11 provide row address.
3) BA0, BA1 provide bank address, A0 - A8 provide column address; A10 HIGH enables the Auto Precharge feature (non
persistent), A10 LOW disables the Auto Precharge feature.
4) This command is BURST TERMINATE if CKE is HIGH, DEEP POWER DOWN if CKE is LOW. The BURST TERMINATE
command is defined for READ or WRITE bursts with Auto Precharge disabled only.
5) A10 LOW: BA0, BA1 determine which bank is precharged.
A10 HIGH: all banks are precharged and BA0, BA1 are “Don’t Care”.
6) This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7) Internal refresh counter controls row and bank addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8) BA0, BA1 select either the Mode Register (BA0 = 0, BA1 = 0) or the Extended Mode Register (BA0 = 0, BA1 = 1); other
combinations of BA0, BA1 are reserved; A0 - A11 provide the op-code to be written to the selected mode register.
9) DQM LOW: data present on DQs is written to memory during write cycles; DQ output buffers are enabled during read
cycles;
DQM HIGH: data present on DQs are masked and thus not written to memory during write cycles; DQ output buffers are
placed in High-Z state (two clocks latency) during read cycles.
2)
3)
4)
L
L
L
L
H
L
L
H
X
X
Code
X
5)
6)7)
L
–
–
L
–
–
L
–
–
L
–
–
X
L
H
Op-Code
–
–
8)
9)
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