參數(shù)資料
型號(hào): HB52RD328DC
廠商: Hitachi,Ltd.
英文描述: 256 MB Unbuffered SDRAM S.O.DIMM(256 MB 未緩沖同步DRAM S.O.DIMM)
中文描述: 256 MB的無(wú)緩沖內(nèi)存的SODIMM(256 MB的未緩沖同步內(nèi)存的SODIMM)
文件頁(yè)數(shù): 52/68頁(yè)
文件大?。?/td> 885K
代理商: HB52RD328DC
HB52RD328DC-F
52
Mode register set to Bank-active command interval:
The interval between setting the mode register and
executing a bank-active command must be no less than l
RSA
.
CK
Command
Address
Mode
Register Set
Bank
Active
MRS
ACTV
I
RSA
BS & ROW
CODE
DQMB Control
The DQMB mask the DQ data. The timing of DQMB is different during reading and writing.
Reading:
When data is read, the output buffer can be controlled by DQMB. By setting DQMB to Low, the
output buffer becomes Low-Z, enabling data output. By setting DQMB to High, the output buffer becomes
High-Z, and the corresponding data is not output. However, internal reading operations continue. The
latency of DQMB during reading is 2 clocks.
Writing:
Input data can be masked by DQMB. By setting DQMB to Low, data can be written. In addition,
when DQMB is set to High, the corresponding data is not written, and the previous data is held. The latency
of DQMB during writing is 0 clock.
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