參數(shù)資料
型號(hào)： HB52RD328DC
廠(chǎng)商： Hitachi,Ltd.
英文描述： 256 MB Unbuffered SDRAM S.O.DIMM(256 MB 未緩沖同步DRAM S.O.DIMM)
中文描述： 256 MB的無(wú)緩沖內(nèi)存的SODIMM（256 MB的未緩沖同步內(nèi)存的SODIMM）
文件頁(yè)數(shù)： 35/68頁(yè)
文件大小： 885K
代理商： HB52RD328DC
HB52RD328DC-F
35
Operation of the SDRAM module
Read/Write Operations
Bank active:
Before executing a read or write operation, the corresponding bank and the row address must be
activated by the bank active (ACTV) command. Bank 0, bank 1, bank 2 or bank 3 is activated according to
the status of the bank select address (BA) pin, and the row address (AX0 to AX11) is activated by the A0 to
A11 pins at the bank active command cycle. An interval of t
RCD
is required between the bank active command
input and the following read/write command input.
Read operation:
A read operation starts when a read command is input. Output buffer becomes Low-Z in
the (
CE
Latency - 1) cycle after read command set. The SDRAM module can perform a burst read operation.
The burst length can be set to 1, 2, 4, 8 or full-page. The start address for a burst read is specified by the
column address and the bank select address (BA) at the read command set cycle. In a read operation, data
output starts after the number of clocks specified by the
CE
Latency. The
CE
Latency can be set to 2 or 3.
When the burst length is 1, 2, 4 or 8, the Dout buffer automatically becomes High-Z at the next clock after the
successive burst-length data has been output.
The
CE
latency and burst length must be specified at the mode register.
CE
Latency
READ
CK
Command
Dout
ACTV
Row
Column
Address
CL = 2
CL = 3
out 0
out 1
out 2
out 3
out 0
out 1
out 2
out 3
t
RCD
CL =
CE
latency
Burst Length = 4
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HB52RD328DC-A6F 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:x64 SDRAM Module
HB52RD328DC-A6FL 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:x64 SDRAM Module
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