參數(shù)資料
型號(hào)： HB52RD328DC
廠商： Hitachi,Ltd.
英文描述： 256 MB Unbuffered SDRAM S.O.DIMM(256 MB 未緩沖同步DRAM S.O.DIMM)
中文描述： 256 MB的無(wú)緩沖內(nèi)存的SODIMM（256 MB的未緩沖同步內(nèi)存的SODIMM）
文件頁(yè)數(shù)： 22/68頁(yè)
文件大小： 885K
代理商： HB52RD328DC
HB52RD328DC-F
22
Pin Functions
CK0/CK1 (input pin):
CK is the master clock input to this pin. The other input signals are referred at CK
rising edge.
S0
/
S1
(input pin):
When
S
is Low, the command input cycle becomes valid. When
S
is High, all inputs are
ignored. However, internal operations (bank active, burst operations, etc.) are held.
RE
,
CE
and
W
(input pins):
Although these pin names are the same as those of conventional DRAM
modules, they function in a different way. These pins define operation commands (read, write, etc.)
depending on the combination of their voltage levels. For details, refer to the command operation section.
A0 to A11 (input pins):
Row address (AX0 to AX11) is determined by A0 to A11 level at the bank active
command cycle CK rising edge. Column address (AY0 to AY7) is determined by A0 to A7 level at the read
or write command cycle CK rising edge. And this column address becomes burst access start address. A10
defines the precharge mode. When A10 = High at the precharge command cycle, both banks are precharged.
But when A10 = Low at the precharge command cycle, only the bank that is selected by A12/A13 (BA) is
precharged.
A12/A13 (input pin):
A12/A13 is a bank select signal (BA). The memory array is divided into bank0,
bank1, bank2 and bank3. If A12 is Low and A13 is Low, bank0 is selected. If A12 is High and A13 is Low,
bank1 is selected. If A12 is Low and A13 is High, bank2 is selected. If A12 is High and A13 is HIgh, bank3
is selected.
CKE0, CKE1 (input pin):
This pin determines whether or not the next CK is valid. If CKE is High, the
next CK rising edge is valid. If CKE is Low, the next CK rising edge is invalid. This pin is used for power-
down mode, clock suspend mode and self refresh mode.
DQMB0 to DQMB7 (input pins):
Read operation: If DQMB is High, the output buffer becomes High-Z. If
the DQMB is Low, the output buffer becomes Low-Z (The latency of DQMB during reading is 2 clocks).
Write operation: If DQMB is High, the previous data is held (the new data is not written). If DQMB is Low,
the data is written (The latency of DQMB during writing is 0 clock).
DQ0 to DQ63 (DQ pins):
Data is input to and output from these pins.
V
CC
(power supply pins):
3.3 V is applied.
V
SS
(power supply pins):
Ground is connected.
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參數(shù)描述
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