參數(shù)資料
型號: HB52RD328DC
廠商: Hitachi,Ltd.
英文描述: 256 MB Unbuffered SDRAM S.O.DIMM(256 MB 未緩沖同步DRAM S.O.DIMM)
中文描述: 256 MB的無緩沖內(nèi)存的SODIMM(256 MB的未緩沖同步內(nèi)存的SODIMM)
文件頁數(shù): 44/68頁
文件大?。?/td> 885K
代理商: HB52RD328DC
HB52RD328DC-F
44
Write command to Read command interval:
1. Same bank, same ROW address:
When the read command is executed at the same ROW address of the
same bank as the preceding write command, the read command can be performed after an interval of no less
than 1 clock. However, in the case of a burst write, data will continue to be written until one cycle before the
read command is executed.
WRITE to READ Command Interval (1)
CK
Command
Din
WRIT
READ
in A0
out B1
out B2
out B3
out B0
Dout
Column = A
Write
Column = B
Read
Column = B
Dout
CE
Latency
DQMB
Burst Write Mode
CE
Latency = 2
Burst Length = 4
Bank 0
WRITE to READ Command Interval (2)
CK
Command
Din
WRIT
READ
in A0
out B1
out B2
out B3
out B0
Dout
Column = A
Write
Column = B
Read
Column = B
Dout
CE
Latency
in A1
DQMB
Burst Write Mode
CE
Latency = 2
Burst Length = 4
Bank 0
2. Same bank, different ROW address:
When the ROW address changes, consecutive read commands
cannot be executed; it is necessary to separate the two commands with a precharge command and a bank-
active command.
3. Different bank:
When the bank changes, the read command can be performed after an interval of no less
than 1 clock, provided that the other bank is in the bank-active state. However, in the case of a burst write,
data will continue to be written until one clock before the read command is executed (as in the case of the
same bank and the same address).
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