參數(shù)資料
型號(hào)： GM5060-H
廠(chǎng)商： Electronic Theatre Controls, Inc.
英文描述： GRAPHICS PROCESSING IC PROVIDING HIGH QUALITY IMAGES FOR LCD MONITORS
中文描述： 圖形處理芯片提供高品質(zhì)的圖像液晶顯示器
文件頁(yè)數(shù)： 75/85頁(yè)
文件大?。?/td> 1375K
代理商： GM5060-H
Genesis Microchip
gm5060 / gm5060-H Data Sheet
February 2002
C5060-DAT-01G
67
HCLK
HCLK is the clock by which data is loaded into, or read from the host interface. HCLK is active
low; the gm5060 captures on the falling edge and transmits on the rising edge of HCLK.
HDATA[3:0]
HDATA[3:0] contains the data that is written to, and read from the host interface. This is a bi-
directional data bus, and thus must be tri-stated by the master device whenever reading from the
gm5060. Each line on this bi-directional bus requires a pull-up resistor.
The serial interface port operates as a slave device and is uniquely addressed by the HFSn input.
The HFSn signal must be de-asserted during a Hardware Reset (i.e. when RESETn is asserted). A
master device initiates a data transfer by asserting HFSn (START) and terminated by de-asserting
HFSn (STOP). HCLK must be inactive for no less than HCLK cycle before HFSn is asserted
and after HFSn is de-asserting. The HFSn signal must be de-asserted for a minimum of a half
cycle between transfers.
A data transfer consists of a number of sequentially transmitted bytes, sent four bits at a time on
HDATA[3:0], formatted as shown in the figures below. Bytes are transferred on the HDATA
lines with the most significant bit (MSB) first. The number of bytes that can be transmitted per
transfer is unrestricted. The protocol supports static operation, and can be halted or started by
controlling the HCLK at any time during a transfer.
4.18.2.1. Command Format
The data transfers using the 6-Wire protocol consist of an instruction byte indicating the type of
operation to be performed by the gm5060. Table 15 above lists the instruction codes and the type
of transfer operation. The content of bytes that follow the instruction byte will vary depending on
the instruction chosen.. All operation modes and instruction codes are identical to those of the 2-
Wire protocol. See Section 4.18.1. No data acknowledge is implemented in the 6-Wire protocol.
It is the responsibility of the external controller to verify, via transfer operations, that data is
received and transmitted correctly.
4.18.2.2. 6-Wire Protocol
The data transfer formats following the instruction byte are identical to 2-wire with the following
exceptions:
The HFSn signal is used for direct addressing, therefore no device address byte is sent. The
first byte instead contains the instruction byte indicating the type of operation to be
performed. Figure 58 shows and equivalent Write Address Increment operation. (‘Increment’
Write implies that the register address is incremented after each data byte is read or written,
allowing the user to program a block of sequential addresses, stating only a single starting
address.)
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