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參數(shù)資料
| 型號： | GM5060-H |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | GRAPHICS PROCESSING IC PROVIDING HIGH QUALITY IMAGES FOR LCD MONITORS |
| 中文描述： | 圖形處理芯片提供高品質的圖像液晶顯示器 |
| 文件頁數(shù)： | 57/85頁 |
| 文件大?。?/td> | 1375K |
| 代理商： | GM5060-H |
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Genesis Microchip
gm5060 / gm5060-H Data Sheet
February 2002
C5060-DAT-01G
49
LOCK EVENT
Input
HS
LOCK LOAD
" X "
" X "
" X "
" Z "
Display
HS
Display
VS
In this example, the Lock Load is located at the end of the frame ( 0x7FF, 0x7FF ). The next clock increments the DTG
( 0x000, 0x000 ) and generates a display VS. Note, the last line may be elongated or truncated to a different length - "Z"
- depending on the location of the DTG at the Lock Event.
*Note - All signals are active "HIGH"
Figure 39. Lock Event Timing (Frame Sync Mode)
Using Frame Sync Mode With and Without Frame Rate Conversion
When frame rate conversion is not being performed, display frames can be synchronized with
input frames once every input frame.
When frame rate conversion is being performed, the display is synchronized to the input every
‘N’ input fields/frames, where ‘N’ is an integer. For example, if converting from XGA 75Hz to
XGA 60Hz (5/4 input/output ratio), synchronization should occur every five input frames.
Note: The Genesis Microchip standard firmware provides a formula to determine the optimum
Lock Event location.
4.13.2.3. Manual Synchronization
The gm5060 Display Timing Generator (DTG) may be forced to the lock load values by asserting
the DFSYNCn pin. This may be thought of as a “manual” lock event. This manual mechanism
is separately enabled via a host register bit. This feature is provided by complex configurations
such as slaving gm5060 timing to other devices.
4.13.3 Display Port Timing
Display timing signals provide timing information so the Display Port can be connected to an
external display device. Based on values programmed in registers, the Display Output Port
produces the horizontal sync (DHS), vertical sync (DVS), and data enable (DEN) control signals.
The figure below provides the registers that define the output display timing.
Horizontal values are programmed in single pixel increments relative to the leading edge of the
horizontal sync signal. Vertical values are programmed in line increments relative to the leading
edge of the vertical sync signal.
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