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參數(shù)資料
| 型號： | GM5060-H |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | GRAPHICS PROCESSING IC PROVIDING HIGH QUALITY IMAGES FOR LCD MONITORS |
| 中文描述： | 圖形處理芯片提供高品質(zhì)的圖像液晶顯示器 |
| 文件頁數(shù)： | 74/85頁 |
| 文件大?。?/td> | 1375K |
| 代理商： | GM5060-H |
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Genesis Microchip
gm5060 / gm5060-H Data Sheet
February 2002
C5060-DAT-01G
66
moments when the transmitting device must release the SDA line and waits for an
acknowledgement from the master receiver.
Note that on the last byte read, no acknowledgement is issued to terminate the transfer.
DATA
DEVICE ADDRESS
DATA
DATA
START
ACK
ACK
OPERATION CODE
START
SDA
SCL
STOP
DEVICE ADDRESS
REGISTER ADDRESS
R/W
ACK
R/W
ACK
ACK
Figure 56. Read Address Increment and Read Address No Inc (0x90 & 0xA0)
Direct Read
It is also possible to perform a read as illustrated below. The internal address will only increment
after each byte if the previous operation code was an incremented operation, i.e., the previous
operation state is retained.
DATA
DEVICE ADDRESS
DATA
DATA
START
SDA
SCL
STOP
R/W
ACK
ACK
Figure 57. Direct Read
4.18.2 6-Wire Configuration
The 6-wire interface connection features four bi-directional data lines HDATA[3:0], one clock
(HCLK), and one chip select / framing signal (HFSn). Four bits are transferred on each clock edge.
The gm5060 operates as a slave on the interface with the external MCU expected to generate
HCLK.
This configuration provides the maximum transfer rate, operating up to 1/20
th
the selected internal
OCM_CLK. The OCM_CLK typically operates at 100MHz, thus allowing a HCLK frequency
of 5 MHz. This presents a maximum 20 Mbit/second data transfer. This configuration is
strongly recommended for complex OSDs or multiple font sets.
Protocol selection is performed during power-up at the rising edge of RESETn input. The 6-Wire
protocol is selected via a bootstrap configuration (HOST_PROTOCOL (FSADDR7) = “1”.)
HFSn
The host framing signal is a master enable for the host interface. If HFSn is de-asserted (high),
then all activity on the remaining signals shall be ignored. If the HFSn is asserted (low), the host
interface responds to bus activity. The assertion of HFSn marks the START condition upon
which the host interface is initialized, and the de-assertion of HFSn marks the end condition upon
which all pending operations are cleared.
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