
Genesis Microchip
gm5060 / gm5060-H Data Sheet
February 2002
C5060-DAT-01G
13
4
4
.
.
1
1
C
C
l
l
o
o
c
c
k
k
i
i
n
n
g
g
O
O
p
p
t
t
i
i
o
o
n
n
s
s
The gm5060 features four clock inputs:
1)
Timing Clock (TCLK). This is a required clock used as a reference frequency source for
the gm5060. Additional clocks are synthesized internally using this reference. TCLK
may be connected to a crystal resonator or external oscillator and is further described
below.
2)
DVI Differential Input Clock (RC+ and RC-). Provided by the external DVI interface.
3)
Video Clock (VCLK) input pin. Provided by the external video decoder.
4)
Host Interface Transfer Clock (HCLK for 6-Wire nibble; SCL for 2-wire serial). Provided
by the external micro controller (MCU).
4.1.1 TCLK Requirements
The TCLK may be generated using either a crystal resonator circuit (recommended) or an
external clock oscillator. The TCLK frequency should range between 14 and 50 MHz, though 24
MHz is preferred.
If TCLK is derived from a crystal resonator, an internal oscillator circuit generates a very low
jitter and low harmonic clock within the gm5060. The crystal should be connected between the
XTAL and TCLK pins and utilize appropriately sized loading capacitors. C
L1
and C
L2
are
terminated to AVDD_33 to increase the power supply rejection ratio. This is shown in the
diagram below.
XTAL
TCLK
OSC_OUT
TCLK Distribution
gm5060
J4
H4
Vdd
180 uA
100 K
C
L1
(5pF typ)
C
L2
(5pF typ)
AVDD_33
AVDD_33
Figure 4.
TCLK connection (with Crystal Resonator)
The size of C
L1
and C
L2
are determined from the crystal manufacturer’s specification and the
parasitic capacitance of the gm5060 and PCB traces. To avoid start up problems with the internal
oscillator, the C
LOAD
parameter specified by the crystal manufacturer should not be exceeded.
C
LOAD
includes C
L1,
C
L2
as well as the parasitic capacitances. Specifically, these include the