參數(shù)資料
型號(hào)： GM5060-H
廠商： Electronic Theatre Controls, Inc.
英文描述： GRAPHICS PROCESSING IC PROVIDING HIGH QUALITY IMAGES FOR LCD MONITORS
中文描述： 圖形處理芯片提供高品質(zhì)的圖像液晶顯示器
文件頁(yè)數(shù)： 41/85頁(yè)
文件大?。?/td> 1375K
代理商： GM5060-H
Genesis Microchip
gm5060 / gm5060-H Data Sheet
February 2002
C5060-DAT-01G
33
measurements. In the case the edges are nearly coincident, the HSYNC signal may be optionally
delayed by 16 clock cycles to avoid any jitter in the results.
4.7.1.1. Format Change Detection
The IFM is able to detect changes in the input format relative to the last measurement and then
alert both the system and the embedded microprocessor. The microprocessor sets a measurement
difference threshold separately for horizontal and vertical timing. If the current field / frame
timing is different from the previously captured measurement by an amount exceeding this
threshold, a status bit is set. An interrupt can also be programmed to occur.
4.7.1.2. Watchdog
The watchdog monitors input VSYNC / HSYNC. When any HSYNC period exceeds the
programmed timing threshold (in terms of the selected IFM_CLK), a register bit is set. When any
VSYNC period exceeds the programmed timing threshold (in terms HSYNC pulses), a second
register bit is set. An interrupt can also be programmed to occur. These watchdog status bits are
used to identify if the input source has been removed.
4.7.1.3. Internal Odd/Even Field Detection (For Interlaced Inputs to ADC Only)
The IFM has the ability to perform field decoding of interlaced inputs to the ADC. The user
specifies start and end values to outline a “window” relative to HSYNC. If the VSYNC leading
edge occurs within this window, the IFM signals the start of an ODD field. If the VSYNC
leading edge occurs outside this window, an EVEN field is indicated (the interpretation of odd
and even can be reversed). The window start and end points are selected from a predefined set of
values.
For ADC interlaced inputs, the gm5060 may be programmed to automatically determine the field
type (even or odd) from the VSYNC/HSYNC relative timing.
HS
window
VS - even
VS - odd
Window
Start
Window End
Figure 26. ODD/EVEN Field Detection
Note: ITU-R BT656 inputs do not require the above field detection feature; the field type is
embedded in the data stream.
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