參數(shù)資料
型號(hào)： GM5060-H
廠商： Electronic Theatre Controls, Inc.
英文描述： GRAPHICS PROCESSING IC PROVIDING HIGH QUALITY IMAGES FOR LCD MONITORS
中文描述： 圖形處理芯片提供高品質(zhì)的圖像液晶顯示器
文件頁數(shù)： 55/85頁
文件大小： 1375K
代理商： GM5060-H
Genesis Microchip
gm5060 / gm5060-H Data Sheet
February 2002
C5060-DAT-01G
47
4.13.1.1. Open Loop Operation
In open loop operation, the display clock (DCLK) is created without consideration to the input
clock (IP_CLK in the above diagram). The DDDS acts as a frequency synthesizer with 30-bits of
resolution and using RCLK as a reference. By using the DCLK PLL and DCLK output divider,
any DCLK frequency between 10 MHz and 135 MHz can be generated.
The DDDS generally operates in this condition to produce valid display timing in the absence of
any input. This allows for example, an OSD to be displayed.
4.13.1.2. Closed Loop Operation
In closed loop, the Display DDS creates an optimal display clock frequency by scaling the input
clock (from any of analog, digital or video sources). The display clock is scaled using the
following relationship:
source.
the
of
rate
refresh
vertical
the
is
N
display.
the
of
rate
refresh
vertical
the
is
M
source.
in the
lines
of
number
total
the
is
SrcVTOTAL
display.
in the
lines
of
number
total
the
is
DispVTOTAL
source.
in the
pixels
of
blanking)
(including
number
total
the
is
SrcHTOTAL
display.
in the
pixels
of
blanking)
(including
number
total
the
is
DispHTOTAL
clock.
input
the
of
frequency
the
is
f(IP_CLK)
clock.
display
the
of
frequency
the
is
f(DCLK)
N
SrcVTOTAL
×
SrcHTOTAL
M
×
DispVTOTAL
×
DispHTOTAL
f(IP_CLK)
=
f(DCLK)
M
×
DispVTOTAL
×
DispHTOTAL
×
f(DCLK)
1
N
SrcVTOTAL
×
SrcHTOTAL
×
f(IP_CLK)
1
Where
×
×
=
×
In other words by programming the number of display pixels (DispHTOTAL), display lines
(DispVTOTAL) and ratio of display frames(M) to source frames(N), the DDDS will synthesize
the correct display clock frequency to satisfy the above relationship.
4.13.2 Display Synchronization
The gm5060 supports two display synchronization modes:
Free Run Mode:
No synchronization. This mode is used when there is no valid input
timing, or for testing purposes.
Frame Sync Mode:
The display frame rate is synchronized to the input frame or field
rate. This mode is used in most cases – with or without frame rate conversion.
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