參數(shù)資料
型號： GM5060-H
廠商： Electronic Theatre Controls, Inc.
英文描述： GRAPHICS PROCESSING IC PROVIDING HIGH QUALITY IMAGES FOR LCD MONITORS
中文描述： 圖形處理芯片提供高品質(zhì)的圖像液晶顯示器
文件頁數(shù)： 54/85頁
文件大小： 1375K
代理商： GM5060-H
Genesis Microchip
gm5060 / gm5060-H Data Sheet
February 2002
C5060-DAT-01G
46
4
4
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.
1
1
3
3
D
D
i
i
s
s
p
p
l
l
a
a
y
y
T
T
i
i
m
i
i
n
n
g
g
a
a
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d
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C
C
o
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Image
Capture
YUV
RealColor
Controls
RGB
Color
Controls
Frame Rate
Conversion
Zoom/
Shrink
Scaling
Triple
ADC
DVI
Rx
ITU656
Decoder
Gamma
Correction
LUT
HDCP
Image
Measurement
Display Timing
& Control
OSD
Frame
Store
Interface
Micro-
processor
(MCU)
Host
Interface
SDRAM
Interface
Analog
RGB
Digital
DVI
Digital YUV
Video
(8-bits)
Serial
Interface
Panel
Interface
.
Clock
Recovery
Input
Color
LUT
(24/48-bits)
Display
Clock
Generation
Figure 37. Display Timing and Control Blocks
The Display Output Port provides data and control signals that permit the gm5060 to connect to a
variety of flat panel or CRT devices. The output interface is configurable for 18 or 24-bit RGB
pixels, either single or double pixel wide. All display data and timing signals are synchronous
with the DCLK output clock.
4.13.1 Display Clock Generation – Display Digital Direct Synthesis Block (DDDS)
The Display DDS is responsible for generating the display clock frequency. The DDDS can
operate in two different configurations: Open loop and Closed Loop FRD (Frequency Ratio
Detector) method. The implementation of the DDDS is shown in the following diagram:
10 MHz <= DDDS_CLK <= 30 MHz
40 MHz <= Fout <= 330 MHz
10 MHz <= DCLK <= 135 MHz
DCLK
IP_CLK
DDDS
RCLK
PLL Divider
Divide by:
(PLL_DIVDE + 1)
PFD
Fout
Filter
VCO
PLL Prescaler
Divide by:
(Prescale_En + 1)
Output Divider
Divide by:
2
OUT_DIV
(Divide by 1 if
OUT_DIV = 0)
DDDS_CLK
FRD
Figure 38. DDDS Block
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