
Genesis Microchip
gm5060 / gm5060-H Data Sheet
February 2002
C5060-DAT-01G
41
devices needed and the possible DRAM configurations. The output is assumed to be UXGA
60Hz.
Table 13. Framestore Bandwidth and Data Widths
DRAM Configuration
Input
Format
Input
Pixel Clock
Required
DRAM
Storage
(1)
Required
DRAM Bandwidth
(Average)
Speed
(3)
Data
Width
Devices
UXGA 60Hz
162 MHz
44.0 Mbits
5478 Mbits/s
132 MHz
48 bits
1 @ 1M x 16 and 1 @ 1M x 32
OR
3 @ 1M x 16
NOTE 1: The input is assumed to be “single-buffered” in the DRAM
NOTE 2: The display frame rate is assumed to be 60 Hz.
NOTE 3: Internal FIFOs are used to line spread and reduce bandwidth requirements. This allows for a 132 MHz FCLK.
The FCLK PLL synthesizes the F_CLK to drive the FRC logic and Framestore Interface
Clock. The FCLK PLL must be programmed such that: F_CLK < (DCLK x 3). This
restriction should impose no functional limitations.
4.10.4 SDRAM Power On Sequence
SDRAM devices have a power-on sequence that must be performed before they can be reliably
accessed. This consists of a pre-charge cycle, 20 refresh cycles, and a MRS cycle. (The MRS –
mode register setting – programs the DRAM for burst size, access latency, etc.) The gm5060
automatically performs this sequence.
4.10.5 SDRAM Power Down
SDRAM devices typically have a low power, non-operational mode. The gm5060 supports this
feature by providing a power down sequence controller, enabled via a host-programmed register.
This feature should always be used before disabling the framestore interface. A soft reset is
required after bringing the SDRAMs back from power-down mode.
4.10.6 Pan and Crop Operations
Pan and Crop is a function that may be implemented in the Active Window Decoder or via the
frame store controller. The frame store controller may be programmed to extract a rectangular
portion of the stored image. This rectangular portion of the image may be displayed at native
resolution, or scaled to the display resolution. Note that frame tear may result if a single frame
buffer is used.