參數(shù)資料
型號： GM5060-H
廠商： Electronic Theatre Controls, Inc.
英文描述： GRAPHICS PROCESSING IC PROVIDING HIGH QUALITY IMAGES FOR LCD MONITORS
中文描述： 圖形處理芯片提供高品質(zhì)的圖像液晶顯示器
文件頁數(shù)： 72/85頁
文件大?。?/td> 1375K
代理商： GM5060-H
Genesis Microchip
gm5060 / gm5060-H Data Sheet
February 2002
C5060-DAT-01G
64
The 2-Wire protocol requires a 7-bit device identification address. 2-Wire mode is selected by
boot-stapping HOST_PROTOCOL (FSADDR7) to “0” and providing the device identification
address on FSADDR[6:0]) on the rising edge of RESETn.
4.18.1.1. Host Interface Command Format
Transactions on the 2-wire host protocol occurs in integer multiples of bytes (i.e. 8 bits or two
nibbles respectively). These form an instruction byte (described in Table 15), a device register
address and/or one or more data bytes.
The first byte of each transfer indicates the type of operation to be performed by the gm5060.
The table below lists the instruction codes and the type of transfer operation. The content of bytes
that follow the instruction byte will vary depending on the instruction chosen. By utilizing these
modes effectively, registers can be quickly configured.
The LSB of the instruction code, denoted ‘A8’ in Table 15 below, is bit 8 of the internal register
address respectively. It is set to ‘0’ to select a starting register address of less than 256 (0x00
through 0xFF), or ‘1’ to select an address greater than 255 (0x100 through 0x1FF). This bit of
the address increments in Address Increment transfers. The unused bits in the instruction byte
should be set to ‘1’.
Table 15. Instruction Byte Map
Operation Mode
Value
7 6 5 4 3 2 1 0
0 0 0 1 x x x A8 Write Address Increment
0 0 1 0 x x x A8 Write Address No Increment
(for table loading)
Description
Allows the user to write a single or multiple bytes to a
specified starting address location. A Macro operation
will cause the internal address pointer to increment
after each byte transmission. Termination of the
transfer will cause the address pointer to increment to
the next address location.
Allows the user to read multiple bytes from a specified
starting address location. A Macro operation will
cause the internal address pointer to increment after
each read byte. Termination of the transfer will cause
the address pointer to increment to the next address
location.
1 0 0 1 x x x A8 Read Address Increment
1 0 1 0 x x x A8 Read Address No Increment
(for table reading)
0 0 1 1 x x x A8
0 1 0 0 x x x A8
1 0 0 0 x x x A8
1 0 1 1 x x x A8
1 1 0 0 x x x A8
0 0 0 0 x x x A8
0 1 0 1 x x x A8
0 1 1 0 x x x A8
0 1 1 1 x x x A8
1 1 0 1 x x x A8
1 1 1 0 x x x A8
1 1 1 1 x x x A8
Reserved
Spare
No operation will be performed
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