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| 型號(hào)： | GM5060-H |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | GRAPHICS PROCESSING IC PROVIDING HIGH QUALITY IMAGES FOR LCD MONITORS |
| 中文描述： | 圖形處理芯片提供高品質(zhì)的圖像液晶顯示器 |
| 文件頁(yè)數(shù)： | 15/85頁(yè) |
| 文件大?。?/td> | 1375K |
| 代理商： | GM5060-H |
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Genesis Microchip
gm5060 / gm5060-H Data Sheet
February 2002
C5060-DAT-01G
7
Table 3.
Description
RCLK and FCLK PLL Signals
Name
I/O
Ball#
TCLK
O
J4
Feedback connection to crystal. If the reference clock source is a clock oscillator, this pin should be
grounded through a 2.7K pulldown resistor.
XTAL
I
H4
Crystal/oscillator input. For crystal, the frequency restrictions are: Min = 14MHz Max = 50MHz. For
oscillator, Min = 14 MHz, Max = 24 MHz [3.3V level]
Table 4.
Description
Video Input Port Signals
Name
I/O
Ball#
VCLK
I
A12
Input sample clock (27MHz) from video decoder. [Input, 5V-tolerant]
YUV7
YUV6
YUV5
YUV4
YUV3
YUV2
YUV1
YUV0
I
B12
C12
A13
B13
C13
A14
B14
C14
Input YUV data in ITU-R BT656 format with embedded SAV and EAV.
These inputs feature internal pull-downs. Any external pull-ups used on these inputs should not exceed
10k ohms. Larger values run the risk of lowering the input high voltage to a value that would create
large currents in the input pads.
YUV(7:0) incorporate General Purpose Inputs (GPIs) . See Section 4.19.1.
[Input, 100K
pull-down, 5V-tolerant]
Table 5.
Description
Host Controller Interface Signals
Name
I/O
Ball#
HCLK / SCL
I
P1
Host Protocol input clock. HCLK for 6-wire nibble, SCL for 2-wire mode.
[Input, schmitt trigger (400mV typical hysteresis), 5V-tolerant]
Host Protocol framing signal for 6-wire nibble mode. Also used as SDA (open drain) signal for 2-wire
mode. [Bidirectional, 4mA drive output, Schmitt trigger input (400mV typical hysteresis), 5V-tolerant]
Host Protocol data nibble for 6-wire mode. The upper nibble byte(3:0) is transferred first followed by
lower nibble byte(7:4).
[Bidirectional, 8mA drive output, Schmitt trigger input (400mV typical hysteresis), 5V-tolerant]
HFSn / SDA
IO
P2
HDATA3
HDATA2
HDATA1
HDATA0
IO
P3
P4
R1
R2
IRQn
O
R3
Interrupt output pin. May be active drive (active low) or open drain. [8mA drive, 5V-tolerant]
IRQINn / GPIO8
IO
R4
Interrupt input to internal 8051 OCM is active low. OCM interrupt#0. This signal is also GPIO8.
Always open drain when in GPO mode.
[Bidirectional, schmitt trigger input (400mV typical hysteresis), 5V-tolerant, 8mA drive output]
Hardware Reset signals is active low.
[Input, schmitt trigger (400mV typical hysteresis), 5V-tolerant]
External clock. For test purposes only when Display DDS is unused. [Input, 5V-tolerant]
RESETn
I
T1
EXTCLK
I
L3
GPIO0 / PWM0
IO
N1
General purpose input/output signal or PWM0. Open drain option via register bit.
[Bidirectional, 8mA drive output, Schmitt trigger input (400mV typical hysteresis0, 5V-tolerant]
General purpose input/output signal or PWM1. Open drain option via register bit.
[Bidirectional, 8mA drive output, Schmitt trigger input (400mV typical hysteresis0, 5V-tolerant]
General purpose input/output signals. Open drain option via register bit.
[Bidirectional, 8mA drive output, Schmitt trigger input (400mV typical hysteresis0, 5V-tolerant]
General purpose input/output signals. Open drain option via register bit.
[Bidirectional, 8mA drive output, Schmitt trigger input (400mV typical hysteresis0, 5V-tolerant]
General purpose input/output signals. Open drain option via register bit.
[Bidirectional, 8mA drive output, Schmitt trigger input (400mV typical hysteresis0, 5V-tolerant]
General purpose input/output signals. Open drain option via register bit.
[Bidirectional, 8mA drive output, Schmitt trigger input (400mV typical hysteresis0, 5V-tolerant]
GPIO1 / PWM1
IO
M4
GPIO2
IO
M3
GPIO3
IO
M2
GPIO4
IO
M1
GPIO5
IO
L1
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