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| 型號(hào)： | GM5060-H |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | GRAPHICS PROCESSING IC PROVIDING HIGH QUALITY IMAGES FOR LCD MONITORS |
| 中文描述： | 圖形處理芯片提供高品質(zhì)的圖像液晶顯示器 |
| 文件頁(yè)數(shù)： | 48/85頁(yè) |
| 文件大小： | 1375K |
| 代理商： | GM5060-H |
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Genesis Microchip
gm5060 / gm5060-H Data Sheet
February 2002
C5060-DAT-01G
40
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Image
Capture
YUV
RealColor
Controls
RGB
Color
Controls
Frame Rate
Conversion
Zoom/
Shrink
Scaling
Triple
ADC
DVI
Rx
ITU656
Decoder
Gamma
Correction
LUT
HDCP
Image
Measurement
Display Timing
& Control
OSD
Frame
Store
Interface
Micro-
processor
(MCU)
Host
Interface
SDRAM
Interface
Analog
RGB
Digital
DVI
Digital YUV
Video
(8-bits)
Serial
Interface
Panel
Interface
.
Clock
Recovery
Input
Color
LUT
(24/48-bits)
Display
Clock
Generation
Figure 32. Frame Store Interface Blocks
The external frame buffer provides the storage required for the frame rate conversion process and
the integrated OSD. The gm5060 is able to operate with 16Mbit or 64Mbit Synchronous DRAM
(SDRAM) devices and/or 16Mbit or 32Mbit Synchronous Graphics RAM (SGRAM) devices.
The FRC data bus width is typically programmed to 48-bits for UXGA applications.
The Frame Rate Conversion Block may be bypassed for applications not requiring frame rate
conversion. See Section 4.14.
4.10.1 Supported SDRAM Devices
The gm5060 operates seamlessly with commercially available SDRAM / SGRAM devices at
operating frequencies up to 143MHz. Typically, a 132 MHz clock frequency is sufficient for
UXGA LCD Monitor applications. For UXGA operation, the frame store is 48 bits wide (e.g.
three 1Mx16 devices).
4.10.2 Adjustable Frame Store Interface Delays
The interface setup/hold times and propagation delay to the external DRAM can be adjusted.
This is done by programming registers to achieve the timing values indicated in Section 5.2 (IO
timing for FSC).
4.10.3 Frame Store Bandwidth Requirements
All data coming into and flowing out of the gm5060 frame rate converter must pass through the
frame store interface. Therefore, this interface must provide enough bandwidth to support the
combined bandwidth demands of the input and display ports.
The table below summarizes the required memory for single buffering and frame store
bandwidth, not including extra memory required for OSD. It also details the number of memory
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