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參數(shù)資料
| 型號： | GF9330-CBP |
| 廠商： | Gennum Corporation |
| 英文描述： | High Performance HDTV/SDTV Deinterlacer |
| 中文描述： | 高性能高清/標清去隔行掃描 |
| 文件頁數(shù)： | 5/42頁 |
| 文件大?。?/td> | 449K |
| 代理商： | GF9330-CBP |
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GF9330 Data Sheet
5 of 42
Proprietary and Confidential
18283 - 4
June 2004
HOST_EN
E4
I
Host interface enable. When set HIGH, the GF9330 will be configured through
the host interface. On a high to low transition of HOST_EN the GF9330 will
replace all register settings in the host interface with the values present on the
external pins of the device including: STD[4:0], MODE[2:0], FVH_EN, FF_EN
and XVOCLK_SL.
SER_MD
G1
I
Host interface mode selection. Enables serial mode operation when HIGH.
Enables parallel mode operation when LOW.
CS
P2
I
Functions as an active low chip select input for host interface parallel mode
operation. Functions as a serial clock input for host interface serial mode
operation.
DAT_IO[7:0]
R4, R3, R2, R1, T4, T3,
T2, T1
I/O
Host interface bi-directional data bus for parallel mode. In serial mode, DAT[7]
serves as the serial data output pin and DAT[0] serves as the serial data input
pin.
R_W
P3
I
Host interface Read/Write control for parallel mode. A read cycle is defined
when HIGH, a write cycle is defined when LOW.
A_D
P1
I
Host interface Address/Data control for parallel mode. The data bus contains
an address when HIGH, a data word when LOW. In serial mode, this pin
serves as the chip select (active low).
VCLK_OUT
A20
O
Video output clock. Output frequency based on selected output standard. See
3.9 Modes of Operation
.
Y1_OUT[11:0]
D18, E20, E19, E18, F20,
F19, F18, F17, G20, G19,
G18, G17
O
Output data bus for separate luminance or multiplexed luminance and colour
difference video data. See
3.10.2 12-bits Output Resolution
.
Y2_OUT[11:0]
H20, H19, H18, H17, J20,
J19, J18, J17, K20, K19,
K18, L18
O
Output data bus for luminance video data during dual pixel mode operation.
See
3.10.2 12-bits Output Resolution
.
C1_OUT[11:0]
L19, L20, M17, M18, M19,
M20, N17, N18, N19, N20,
P17, P18
O
Output data bus for colour difference video data.
See
3.10.2 12-bits Output Resolution
.
C2_OUT[11:0]
P19, P20, R17, R18, R19,
R20, T18, T19, T20, U18,
U19, U20
O
Output data bus for colour difference video data during dual pixel mode
operation. See
3.10.2 12-bits Output Resolution
.
LOCK_32
B20
O
Control signal output. When the GF9330’s internal algorithm detects a 3:2
sequence in the video stream the LOCK_32 signal is set HIGH. Otherwise,
LOCK_32 is LOW.
XSEQ[3:0]
D19, D20, C19, C20
I/O
Control signal input/output. For external 3:2 sequence detection, the
XSEQ[3:0] pins will be used to provide the 3:2 sequence information. For
internal 3:2 detection the XSEQ[3:0] pins output the detected 3:2 sequence
information. See
Figure 3-12: Sequence Detection Input Signals
.
H_OUT
V20
O
Output control signal. H_OUT is HIGH during horizontal blanking.
F_OUT
V19
O
Output control signal. F_OUT is LOW during field 1 and HIGH during field 2.
V_OUT
W20
O
Output control signal. V_OUT is HIGH during vertical blanking.
S1_CLK
Y10
O
SDRAM bank 1 clock.
S1_CS
Y3
O
Active low SDRAM chip select for Field Buffer 1.
Table 1-1: Pin Descriptions (Continued)
Symbol
Pin Grid
Type
Description
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相關(guān)代理商/技術(shù)參數(shù) |
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| GF9331 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:GF9331 - HDTV/SDTV Motion Co-processor |
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| GF9410\5B | 功能描述:MOSFET N-Channel 30V 2A RoHS:否 制造商:STMicroelectronics 晶體管極性:N-Channel 汲極/源極擊穿電壓:650 V 閘/源擊穿電壓:25 V 漏極連續(xù)電流:130 A 電阻汲極/源極 RDS（導通）:0.014 Ohms 配置:Single 最大工作溫度: 安裝風格:Through Hole 封裝 / 箱體:Max247 封裝:Tube |
| GF9450C-CBE3 | 制造商:Sigma Designs 功能描述:IC VIDEO PROCESSOR 10BIT 701HSBG |
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