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參數(shù)資料
| 型號： | GF9330-CBP |
| 廠商： | Gennum Corporation |
| 英文描述： | High Performance HDTV/SDTV Deinterlacer |
| 中文描述： | 高性能高清/標(biāo)清去隔行掃描 |
| 文件頁數(shù)： | 16/42頁 |
| 文件大?。?/td> | 449K |
| 代理商： | GF9330-CBP |
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GF9330 Data Sheet
16 of 42
Proprietary and Confidential
18283 - 4
June 2004
3.2.2.4 V_OFFSET_ODD
This defines the number of lines from the V_IN pin EAV transition to the end of the
odd active video field region. This parameter has a maximum value of 255. Eight
bits within the host interface are dedicated to this parameter. This parameter has
been added to accommodate all video decoders which that output non-standard
timing for the V_IN signal. See
Figure 3-2: Vertical Offset Definition
.
Figure 3-2: Vertical Offset Definition
3.2.2.5 V_OFFSET_EVEN
This parameter defines the number of lines from the V_IN pin EAV transition to the
end of the even active video field region. This parameter has a maximum value of
255. Eight bits within the host interface are dedicated to this parameter. This
parameter has been added to accommodate all video decoders that output non-
standard timing for the V_IN signal. See
Figure 3-2: Vertical Offset Definition
.
3.2.2.6 F_OFFSET_ODD
This defines the number of lines from the F_IN pin EAV transition to the vertical
blanking interval following the odd field. This parameter has a maximum value of
255. Eight bits within the host interface are dedicated to this parameter. This
parameter has been added to accommodate all video decoders that output non-
standard timing for the F_IN signal. See
Figure 3-1: Generic Input Format
Definition
.
3.2.2.7 F_OFFSET_EVEN
This register defines the number of lines from the F_IN pin EAV transition to the
vertical blanking interval following the even field. This parameter has a maximum
value of 255. Eight bits within the host interface are dedicated to this parameter.
This parameter has been added to accommodate all video decoders which output
non-standard timing for the F_IN signal. See
Figure 3-1: Generic Input Format
Definition
.
3.2.2.8 H_POLARITY
This register defines the polarity of the H_IN pin. With H_POLARITY set LOW, a
falling transition on the H_IN pin indicates end of active video. With H_POLARITY
set HIGH, a rising transition on the H_IN pin indicates the end of active video. One
bit within the host interface is dedicated to this parameter.
H_IN
Vertical Blanking Region
V_IN
V_OFFSET_ODD/EVEN
Last active line
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