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參數(shù)資料
| 型號： | GF9330-CBP |
| 廠商： | Gennum Corporation |
| 英文描述： | High Performance HDTV/SDTV Deinterlacer |
| 中文描述： | 高性能高清/標清去隔行掃描 |
| 文件頁數(shù)： | 24/42頁 |
| 文件大小： | 449K |
| 代理商： | GF9330-CBP |
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GF9330 Data Sheet
24 of 42
Proprietary and Confidential
18283 - 4
June 2004
3.5.3 Control Register Definitions
The host interface internal registers are divided into three classes: User
Configurable (UC), Auto-Configurable (AC), and Read-Only (RO). Address
locations 0 through 14 contain parameters which may be configured by the user.
Locations 15 through 31 are automatically configured based on the STD[4:0] and
MODE[2:0] registers, but can be user configured if desired.
Address 0 contains three status registers LOCK_32, FF_DETECT, and
SEQUENCE[3:0] which can only be read. Writing to the read-only registers will
have no effect on their contents.
Table 3-5: Control Register Definitions
Address
Bit
Location
Register Name
Class
Description
Default
0
4:0
STD[4:0]
UC
Defines the video standard as described in
3.1 Supported Input
Video Formats
.
00000
7:5
MODE[2:0]
UC
Defines the GF9330 operating mode:
000: Interlaced to Progressive Mode
001: Field Merging Mode
010: Film Rate Down Conversion Mode
011: Film Rate Down Conversion (Progressive Segmented
Frame) Mode
111: Bypass Mode (Video Pass Through Mode)
000
11:8
SEQUENCE[3:0]
RO
Provides the detected field sequence number from the 3:2
detection circuit.
Calculated
12
FF_DETECT
RO
Set to '1' if a video freeze frame has been detected.
Calculated
13
LOCK_32
RO
Set to '1' if a 3:2 video sequence has been detected.
Calculated
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