參數(shù)資料
型號(hào)： GF9330-CBP
廠商： Gennum Corporation
英文描述： High Performance HDTV/SDTV Deinterlacer
中文描述： 高性能高清/標(biāo)清去隔行掃描
文件頁(yè)數(shù)： 38/42頁(yè)
文件大?。?/td> 449K
代理商： GF9330-CBP
GF9330 Data Sheet
38 of 42
Proprietary and Confidential
18283 - 4
June 2004
3.11.1 Internal 3:2 Detection
When set to operate in internal 3:2 detect mode, the GF9330 can automatically
detect a 3:2 pull-down sequence in the incoming video data stream. If a 3:2
sequence is detected, the GF9330 sets the LOCK_32 control bit in the host
interface to ‘1’. The LOCK_32 pin is also asserted HIGH once the sequence has
been detected.
The actual 3:2 sequence information is reported in the SEQUENCE[3:0] register
within the host interface and on the XSEQ[3:0] pins. Refer to
Figure 3-12:
Sequence Detection Input Signals
for a pictorial representation of the 3:2
sequence reporting.
3.11.2 External 3:2 Detection
When set to operate in external mode, the user will supply the 3:2 sequence
information to the XSEQ[3:0] pins. The GF9330 uses this information to properly de-
interlace the input signal or to perform 60Hz to 24Hz conversion depending on the
state of the MODE[2:0] register in the host interface or MODE[2:0] pins.
When operating in this mode the input 3:2 sequence information relates to the input
data stream. The 3:2 sequence information requires updating during the first blank
line of the vertical blanking interval, identifying the sequence number for the
following field.
3.11.3 Sequence Detection and Compensation
The GF9330 supports external 2:2 sequence detection. A LOCK_22 pin is
provided to indicate the presence of a 2:2 sequence. The sequence information is
inherently embedded in the interlaced video input data, and is identified with the
F_IN signal (either derived from the embedded TRSs or supplied from the external
pin). The LOCK_22 signal will be updated during the first line of each vertical
blanking interval.
Table 3-9: 3:2 Mode Select
MODE_32
Description
0
Internal.
The 3:2 sequence is automatically detected in the input data stream. The
GF9330 reports 3:2 lock and 3:2 sequence information in the host interface
registers called LOCK_32 and SEQUENCE[3:0]. The GF9330 also reports this
information on the XSEQ[3:0] pins when configured as outputs.
1
External.
The GF9330 accepts a 3:2 sequence from the XSEQ[3:0] pins configured as
inputs.
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