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參數(shù)資料
| 型號： | GF9330-CBP |
| 廠商： | Gennum Corporation |
| 英文描述： | High Performance HDTV/SDTV Deinterlacer |
| 中文描述： | 高性能高清/標(biāo)清去隔行掃描 |
| 文件頁數(shù)： | 20/42頁 |
| 文件大小： | 449K |
| 代理商： | GF9330-CBP |
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GF9330 Data Sheet
20 of 42
Proprietary and Confidential
18283 - 4
June 2004
3.5.1.2 Auto-Configure
The Auto-Configure feature will be executed when the Auto-Configure control bit is
set. All Auto-Configure registers will be updated to their appropriate settings based
on the current video standard and operational mode.
When setting the Auto-Configure bit, the command word should be set with only
the AC bit set to 1. All of the 15 remaining bits should be set to 0. To complete the
Auto-Configuration 16 additional bits must be loaded into the device. The state of
these bits can be either HIGH or LOW. Before Auto-Configuring the device, the
standard and mode must be set using either the host interface (HOST_EN = 1) or
the external pins (with a falling transition of HOST_EN).
This simplifies configuration while allowing customization of many features and
format parameters.
3.5.1.3 Serial Data Word Description
The serial data word consists of a 16-bit word as shown in
Figure 3-5: Serial Data
Word Bit Representation
. Serial data is transmitted or received MSB first.
Figure 3-5: Serial Data Word Bit Representation
Both command and data words are clocked into the GF9330 on the rising edge of
the serial clock (SCLK), which may operate in either a continuous or burst fashion.
The first bit (MSB) of the serial output (SDO) is available following the last falling
SCLK edge of the "read" command word. The remaining bits are clocked out on
the falling edges of SCLK.
3.5.1.4 Serial Write Operation
All write cycles consist of a command word followed by a data word, both
transmitted to the GF9330 via SDI. The first 16-bit word transmitted following a
falling transition of SCS is a command word. Several write cycles may be
performed while SCS is LOW. See
Figure 3-6: Write Cycle
.
Figure 3-6: Write Cycle
D15
D14
D13
D12
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D11
D10
MSB
LSB
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCLK
SCS
R/W
0
AU
R
A0
A1
A2
A3
A4
R
R
R
R
R
R
R
R
SDI
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
D15 D14 D13
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D12 D11 D10
SDO
tSU_HI
tIH_HI
tSU_HI
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