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參數(shù)資料
| 型號： | GF9330-CBP |
| 廠商： | Gennum Corporation |
| 英文描述： | High Performance HDTV/SDTV Deinterlacer |
| 中文描述： | 高性能高清/標清去隔行掃描 |
| 文件頁數(shù)： | 30/42頁 |
| 文件大小： | 449K |
| 代理商： | GF9330-CBP |
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GF9330 Data Sheet
30 of 42
Proprietary and Confidential
18283 - 4
June 2004
3.6 Closed Caption Blanking
The GF9330 provides a blanking function for selected input video lines.
Consecutive lines within each input field are blanked when this function is enabled,
beginning with the CC_BLANK_START_LINE and ending with the
CC_BLANK_END_LINE. The blanking is applied prior to any processing of the
video data.
The blanking function is enabled with the CC_BLANK_EN bit.
BLANK_START_LINE and BLANK_END_LINE are each allocated 8-bits within the
host interface.
3.7 Programmable Noise Reduction and Detail Enhancement
The GF9330 performs an efficient technique for high frequency noise reduction
and detail enhancement. There are 256 levels of control provided by the
NOISE_RED[7:0] bits within the host interface.
High frequency details that are detected with a two-dimensional high pass filter are
enhanced using a non-linear function mapping between input and output signal.
There are 512 levels of control provided by the DETAIL_ENH[9:0] bits within the
host interface.
29
11:0
V_FIELD2_LASTLINE
[11:0]
UC
Defines the last line of the second active video field.
Auto
14:12
A
DD_LINES_TOP_F2
AC
Defines the number of lines to add to the top of field 2 (not
used).
Auto
30
0
EXT_MEMCLK_SEL
AC
Controls the selection of the SDRAM clock source. For
VCLK_IN frequency less than 36 MHz, the internal clock
doubler can be used, in all other modes an external source is
required (MEMCLK_IN).
Auto
1
VOCLK_X1_SEL
AC
Normally set for HD modes where the output video clock is
equal to the input video clock frequency and is set to '0' for SD
cases where the output video clock is double the video input
clock frequency.
Auto
2
CLK_X1_SE
AC
Normally set for all HD modes and is '0' for all other cases.
Auto
31
0
S
TART_OPERATION
UC
Using external F_IN, V_IN and H_IN signals, this parameter
must be set following the completion of programming the F_IN,
V_IN and H_IN offsets.
0
15
CMD_RESET
UC
Forces the GF9330 to enter a reset state. This commanded
reset remains in effect until this parameter is cleared with a
subsequent command.
0
Table 3-5: Control Register Definitions (Continued)
Address
Bit
Location
Register Name
Class
Description
Default
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相關(guān)代理商/技術(shù)參數(shù) |
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