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參數(shù)資料
| 型號： | GF9330-CBP |
| 廠商： | Gennum Corporation |
| 英文描述： | High Performance HDTV/SDTV Deinterlacer |
| 中文描述： | 高性能高清/標(biāo)清去隔行掃描 |
| 文件頁數(shù)： | 10/42頁 |
| 文件大?。?/td> | 449K |
| 代理商： | GF9330-CBP |
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GF9330 Data Sheet
10 of 42
Proprietary and Confidential
18283 - 4
June 2004
Table 2-4: AC Electrical Characteristics - SDRAM Interfaces
The SDRAM 1 Interface signals include S1_CLK, S1_CS, S1_RAS, S1_CAS, S1_WE, S1_ADDR[13:0] and
S1_DAT[47:0].
The SDRAM 2 Interface signals include S2_CLK, S2_CS, S2_RAS, S2_CAS, S2_WE, S2_ADDR[13:0] and
S2_DAT[47:0].
V
DDIO
= 3.0 to 3.6V, V
DDCORE
= 2.25 to 2.75V, T
A
= 0 to 70
o
C, unless otherwise shown.
Parameter
Conditions
Symbol
Min
Typ
Max
Units
Notes
Clock Input Frequency
F
HSCI_SD
-
85
90
MHz
a
Input Data Setup Time
t
SU_SD
2.0
-
-
ns
a
,
b
Input Data Hold Time
t
IH_SD
2.5
-
-
ns
a
,
b
Input Clock Duty Cycle
40
-
60
%
a
Output Data Delay Time
V
DDIO
=3.6V,
C
L
=15pF load
t
OD_SD
-
-
9.1
ns
a
Output Data Hold Time
V
DDIO
=3.6V,
C
L
=15pF load
t
OH_SD
2.0
-
-
ns
a
Output Enable Time
V
DDIO
=3.6V,
C
L
=15pF load
t
OEN_SD
-
-
20
ns
a
,
c
Output Disable Time
V
DDIO
=3.6V,
C
L
=15pF load
t
ODIS_SD
-
-
20
ns
a
,
c
Output Data Rise/Fall Time
V
DDIO
=3.6V,
C
L
=15pF load
t
ODRF_SD
-
-
2.0
ns
a
,
d
a.Based on simulation results, verified during device characterization process.
b.50% levels.
c.Two clock cycles allocated for data bus turnaround.
d.20% to 80% levels.
Table 2-5: AC Electrical Characteristics - Host Interfaces
The Host Interface signals include HOST_EN, SER_MD, CS, DAT_IO[7:0], R_W and A_D.
V
DDIO
= 3.0 to 3.6V, V
DDCORE
= 2.25 to 2.75V, T
A
= 0 to 70
o
C, unless otherwise shown.
Parameter
Conditions
Symbol
Min
Typ
Max
Units
Notes
Clock Input Frequency
F
HSCI_HI
-
-
20
MHz
a
Input Data Setup Time
t
SU_HI
5
-
-
ns
a
,
b
Input Data Hold Time
t
IH_HI
1.5
-
-
ns
a
,
b
Input Clock Duty Cycle
40
-
60
%
a
Output Data Delay Time
V
DDIO
=3.6V,
C
L
=15pF load
t
OD_HI
-
-
10.0
ns
a
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