參數(shù)資料
型號: GF9330-CBP
廠商: Gennum Corporation
英文描述: High Performance HDTV/SDTV Deinterlacer
中文描述: 高性能高清/標(biāo)清去隔行掃描
文件頁數(shù): 17/42頁
文件大?。?/td> 449K
代理商: GF9330-CBP
GF9330 Data Sheet
17 of 42
Proprietary and Confidential
18283 - 4
June 2004
3.2.2.9 F_POLARITY
This register defines the polarity of the F_IN pin. Refer to
Table 3-2: F_POLARITY
for F_POLARITY encoding. One bit within the host interface is dedicated to this
parameter.
3.2.2.10 V_POLARITY
This register defines the polarity of the V_IN pin. With V_POLARITY set LOW, a
falling transition on the V_IN pin indicates the end of active video. With
V_POLARITY set HIGH, a rising transition on the V_IN pin indicates the end of
active video. One bit within the host interface is dedicated to this parameter.
3.3 Seamless Interface to the GF9331 Motion Co-processor for
Directional Filter Control
The GF9330 can operate as a stand-alone motion adaptive de-interlacer or can
operate in conjunction with the GF9331 Motion Co-processor. The GF9331
contains adaptive multi-directional edge detection and vertical motion detection.
Control signals are fed back directly to the GF9330.
These control signals adaptively switch the GF9330’s internal edge & vertical
motion de-interlacing filters on a pixel by pixel basis. These control signals are fed
to the GF9330 by the GF9331 over the FIL_SEL[3:0] control bus. When the
GF9330 is not being used with the GF9331, the FIL_SEL[3:0] inputs should be set
LOW.
NOTE
:
When using the GF9331, the Y_IN[9:0] of the GF9330 must be connected
to Y_OUT[9:0] of the GF9331 and C_IN[9:0] of the GF9330 must be connected to
the C_OUT[9:0] of the GF9331. FIL_SEL[3:0] of the GF9330 must also be
connected to FIL_SEL[3:0] of the GF9331. The timing information from the
GF9331 is provided exclusively through the F_OUT, H_OUT and V_OUT pins
which must be connected to the F_IN, H_IN and V_IN pins of the GF9330.
Table 3-2: F_POLARITY
F_POLARITY Register
F_IN Pin
F_IN Pin Function
0
0
Even Field
0
1
Odd Field
1
0
Odd Field
1
1
Even Field
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