參數(shù)資料
型號(hào)： GF9330-CBP
廠商： Gennum Corporation
英文描述： High Performance HDTV/SDTV Deinterlacer
中文描述： 高性能高清/標(biāo)清去隔行掃描
文件頁(yè)數(shù)： 4/42頁(yè)
文件大?。?/td> 449K
代理商： GF9330-CBP
GF9330 Data Sheet
4 of 42
Proprietary and Confidential
18283 - 4
June 2004
Table 1-1: Pin Descriptions
Symbol
Pin Grid
Type
Description
RESET
A1
I
Active low, asynchronous RESET. Resets all internal logic to default
conditions. Should be applied on power up.
VCLK_IN
F1
I
Video input clock. When the input is SDTV the input clock will be 27, 36, 54 or
72MHz. When the input format is HDTV, the input clock will be 74.25 or 74.25/
1.001MHz.
MEMCLK_IN
H1
I
Memory clock for SDRAM operation to support HD modes, 90MHz input
(supplied by an off-chip crystal oscillator).
XVOCLK_IN
J1
I
External video output clock. This input may be used instead of the internal
VCLK_IN clock doubler to supply the video output clock VCLK_OUT.
XVOCLK_SL
H4
I
Control signal input. When HIGH, selects XVOCLK_IN; when LOW, selects
the internal VCLK_IN clock doubler for generation of the video output
VCLK_OUT signal.
Y_IN[9:0]
B1, C1, C2, C3, D1, D2,
D3, E1, E2, E3
I
10/8-bit input bus for separate luminance or multiplexed luminance and colour
difference video data. When supplying 8-bit data to the GF9330, Y_IN[1:0] will
be set LOW and the 8-bit data supplied to Y_IN[9:2].
C_IN[9:0]
J3, J4, K1, K2, K3, K4, L4,
L3, L2, L1
I
10/8-bit input bus for colour difference for video data. When supplying 8-bit
data to the GF9330, C_IN[1:0] will be set LOW and the 8-bit data supplied to
C_IN[9:2].
FIL_SEL[3:0]
M4, M3, M2, M1
I
Filter selection control bus. FIL_SEL[3:0] are used to switch the GF9330’s
internal directional filters on a pixel by pixel basis. FIL_SEL[3:0] is supplied by
the GF9331.
F_IN
N2
I
Video timing control. F_IN identifies the ODD and EVEN fields in the incoming
video signal. F_IN will be LOW in Field 1 and HIGH in Field 2.
V_IN
N3
I
Video timing control. V_IN represents the vertical blanking signal associated
with the incoming video signal. V_IN is HIGH during the vertical blanking
interval and LOW during active video.
H_IN
N4
I
Video timing control. H_IN represents the horizontal blanking signal
associated with the incoming video signal. H_IN is HIGH during horizontal
blanking and LOW during active video.
FVH_EN
N1
I
Control signal input. When HIGH, the F_IN, V_IN, and H_IN input pins will be
used for video data signalling. When LOW, embedded TRS’s will be detected
for video data timing.
FF_EN
P4
I
Control signal input. When HIGH, FF_EN enables the GF9330’s internal
freeze frame compensation. See
3.11.4 Static and Freeze Frame Detection/
Compensation
.
LOCK_22
J2
I
Control signal input. For 2:2 pull-down compensation, the LOCK_22 pin will be
used to identify the presence of a 2:2 sequence in the input video stream.
STD[4:0]
G2, G3, G4, H2, H3
I
Video format definition. Defines the video standard when operating without the
host interface. See
Table 3-1: Encoding of STD[4:0] for Selecting Input Data
Format
.
MODE[2:0]
F2, F3, F4
I
Operating mode selection. Defines the mode of operation when operating
without the host interface. See
3.9 Modes of Operation
.
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