參數(shù)資料
型號: GF9330-CBP
廠商: Gennum Corporation
英文描述: High Performance HDTV/SDTV Deinterlacer
中文描述: 高性能高清/標清去隔行掃描
文件頁數(shù): 22/42頁
文件大?。?/td> 449K
代理商: GF9330-CBP
GF9330 Data Sheet
22 of 42
Proprietary and Confidential
18283 - 4
June 2004
3.5.2.1 Parallel Address Word Description
The 8-bit address word loads in the address to be accessed and allows the Auto-
Configure bit to be set. The MSB is the Auto-Configure bit, followed by two
reserved bits and a 5-bit address as shown in
Figure 3-9: Parallel Address Word
Bit Representation
.
Figure 3-9: Parallel Address Word Bit Representation
3.5.2.2 Parallel Write Operation
A write cycle to the parallel interface is shown in
Figure 3-10: Write Cycle to the
Parallel Interface
. First an 8-bit address word is provided to the DAT_IO bus by
asserting the R_W pin to LOW and the A_D pin to HIGH. The MSB of the address
word contains an auto-update flag, which allows automatic configuration of
predefined registers. The 5 LSB's of the address word contain the address location
for the read or write operation. The remaining address bits DAT_IO[6:5] are
reserved. The address word is registered on the falling edge of CS. Following this,
the A_D pin is driven LOW and two data words are sent upper byte (UB) word first
and are each clocked in on the falling edge of CS. Two 8-bit data words must follow
each address word to occupy each 16-bit parameter, which are defined in
Figure
3-11: Host Interface Register Allocation
.
Figure 3-10: Write Cycle to the Parallel Interface
3.5.2.3 Parallel Read Operation
A read cycle begins with an address write by asserting the R_W pin LOW and the
A_D pin HIGH. The address is clocked on the falling edge of CS. Following the
address, the R_W pin must be driven HIGH and A_D pin driven LOW to allow the
upper byte of data to be clocked out on the first falling edge of CS followed by the
lower byte on the second falling edge of CS.
AC
RSV
RSV
A4
A0
A1
A3
A2
MSB
LSB
ADDRESS
(UB)
DATA_IN
(LB)
DATA_IN
ADDRESS
DA(UB)
DA(LB)
DAT_IO[7:0]
R_W
A_D
CS
tODIS_HI
tOEN_HI
tSU_HI
tIH_HI
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