參數(shù)資料
型號(hào): EC000UM
英文描述: EC000 Core User's Manual (SCM68000)
中文描述: EC000核心用戶(hù)手冊(cè)(SCM68000)
文件頁(yè)數(shù): 99/145頁(yè)
文件大小: 829K
代理商: EC000UM
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Bus Operation
3-16
EC000 CORE PROCESSOR USER’S MANUAL
MOTOROLA
the SCM68000 inserts wait states (full clock cycles) until either DTACKB or BERRB is as-
serted. Also, on the rising edge of S16, the SCM68000 asserts UDSB or LDSB, and DSB.
CASE WRITE 1: DTACKB is received alone or with BERRB (see 3.4 Bus Error and Halt
STATE 17
During state 17 (S17), no bus signals are altered.
STATE 18
During state 18 (S18), no bus signals are altered.
STATE 19
On the falling edge of the clock entering state 19 (S19), the SCM68000 negates ASB,
UDSB or LDSB, and DSB. As the clock rises at the end of S19, the SCM68000 places the
data bus in the high-impedance state and drives RWB and ERWB to a logic high. The de-
vice negates DTACKB or BERRB at this time.
CASE READ 2: DTACKB and BERRB are received (see 3.4 Bus Error and Halt Opera-
STATE 5
During state 5 (S5), no bus signals are altered.
STATE 6
During state 6 (S6), no bus signals are altered and data from the device is ignored.
STATE 7
During state 7 (S7), UDSB or LDSB, and DSB are negated.
STATES 8–10
The bus signals are unaltered during state 8 (S8) through state 10 (S10).
STATE 11
During state 11 (S11), ASB, is negated. The cycle terminates without the write portion of
the cycle.
CASE READ 3: Only BERRB is received (see 3.4 Bus Error and Halt Operation).
STATES 5–8
The bus signals are unaltered during state 5 (S5) through state 8 (S8).
STATE 9
During state 9 (S9), UDSB or LDSB, and DSB are negated.
STATE 10
During state 10 (S10), no bus signals are altered.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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