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參數(shù)資料
| 型號： | EC000UM |
| 英文描述： | EC000 Core User＇s Manual (SCM68000) |
| 中文描述： | EC000核心用戶手冊（SCM68000） |
| 文件頁數(shù)： | 103/145頁 |
| 文件大?。?/td> | 829K |
| 代理商： | EC000UM |
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Bus Operation
MOTOROLA
EC000 CORE PROCESSOR USER’S MANUAL
3-19
BGB can be routed through a daisy-chained network or through a specific priority-encoded
network. Any method of external arbitration that observes the protocol can be used.
3.2.3 Acknowledgment of Mastership (3-Wire Bus Arbitration Only)
Upon receiving BGB, the requesting device waits until ASB, DTACKB, and BGACKB are
negated before asserting BGACKB. The negation of ASB indicates that the previous bus
master has completed its cycle. (No device is allowed to assume bus mastership while ASB
is asserted.) The negation of BGACKB indicates that the previous master has released the
bus. The negation of DTACKB indicates that the previous slave has terminated the connec-
tion to the previous master. (In some applications, DTACKB might not be included in this
function; general-purpose devices would be connected using ASB only.) When BGACKB is
asserted, the asserting device is bus master until it negates BGACKB. BGACKB should not
be negated until after the bus cycle(s) is complete. A device relinquishes control of the bus
by negating BGACKB.
The bus request from the granted device should be negated after BGACKB is asserted. If
another bus request is pending, BGB is reasserted within a few clocks, as described in 3.3
Bus Arbitration Control. The SCM68000 does not perform any external bus cycles before
reasserting BGB.
Figure 3-15. 2-Wire Bus Arbitration Cycle Flowchart
GRANT BUS ARBITRATION
REQUEST THE BUS
1) ASSERT BUS REQUEST (BRB)
REQUESTING DEVICE
1) NEGATE BUS REQUEST (BRB)
PROCESSOR
1) ASSERT BUS GRANT (BGB)
OPERATE AS BUS MASTER
REARBITRATE OR RESUME
PROCESSOR OPERATION
RELEASE BUS MASTERSHIP
ACKNOWLEDGE RELEASE OF
BUS MASTERSHIP
1) NEGATE BUS GRANT (BGB)
1) EXTERNAL ARBITRATION DETER-
MINES NEXT BUS MASTER
2) NEXT BUS MASTER WAITS FOR
CURRENT CYCLE TO COMPLETE
3) PERFORM DATA TRANSFERS (READ
AND WRITE CYCLES) ACCORDING
TO THE SAME RULES THE PRO-
CESSOR USES
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For More Information On This Product,
Go to: www.freescale.com
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