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參數(shù)資料
| 型號(hào)： | EC000UM |
| 英文描述： | EC000 Core User＇s Manual (SCM68000) |
| 中文描述： | EC000核心用戶手冊(cè)（SCM68000） |
| 文件頁(yè)數(shù)： | 123/145頁(yè) |
| 文件大?。?/td> | 829K |
| 代理商： | EC000UM |
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Bus Operation
3-38
EC000 CORE PROCESSOR USER’S MANUAL
MOTOROLA
mum time between the transition of RWB and the driving of the data bus, which is effectively
the maximum turnoff time for any device driving the data bus.
After the SCM68000 places valid data on the bus, it asserts the data strobe signals. A data
setup time, similar to the address setup time previously discussed, can be used to improve
performance. Parameter #26 is the minimum time a slave device can accept valid data
before recognizing a data strobe. The slave device asserts DTACKB after it accepts the
data. Parameter #25 is the minimum time after negation of the strobes during which the valid
data remains on the address bus. Parameter #28 is the maximum time between the nega-
tion of the strobes by the SCM68000 and the negation of DTACKB by the slave device. If
DTACKB remains asserted past the time specified by parameter #28, the SCM68000 may
recognize it as being asserted early in the next bus cycle and may terminate that cycle pre-
maturely. Figure 3-32 shows the important timing parameters for a pseudo-asynchronous
write cycle.
3.6 SYNCHRONOUS OPERATION
In some systems, external devices use the system clock to generate DTACKB and other
asynchronous input signals. This synchronous operation provides a closely coupled design
with maximum performance, appropriate for frequently accessed parts of the system. For
example, memory can operate in the synchronous mode, but peripheral devices operate
asynchronously. For a synchronous device, the designer uses explicit timing information
shown in Section 7 Electrical Characteristics. These specifications define the state of all
bus signals relative to a specific state of the SCM68000 clock.
The standard SCM68000 bus cycle consists of four clock periods (eight bus cycle states)
and, optionally, an integral number of clock cycles inserted as wait states. Wait states are
Figure 3-32. Pseudo-Asynchronous Write Cycle
A31–A0
ASB
RWB
UDSB and/or LDSB
D15–D0
DTACKB
11
55
22
26
28
25
20A
13
17
and DSB
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For More Information On This Product,
Go to: www.freescale.com
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