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參數(shù)資料
| 型號： | EC000UM |
| 英文描述： | EC000 Core User＇s Manual (SCM68000) |
| 中文描述： | EC000核心用戶手冊（SCM68000） |
| 文件頁數(shù)： | 25/145頁 |
| 文件大?。?/td> | 829K |
| 代理商： | EC000UM |
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MOTOROLA
EC000 CORE PROCESSOR USER’S MANUAL
6-1
SECTION 6
16-BIT INSTRUCTION EXECUTION TIMES
This section contains listings of the instruction execution times in terms of external clock
(CLKI) periods for the SCM68000 (EC000 core)1 in 16-bit mode. In this data, it is assumed
that both memory read and write cycles consist of four clock periods. A longer memory cycle
causes the generation of wait states that must be added to the total instruction times.
The number of bus read and write cycles for each instruction is also included with the timing
data. This data is shown as
n(r/w)
where:
n is the total number of clock periods
r is the number of read cycles
w is the number of write cycles
For example, a timing number shown as 18(3/1) means that the total number of clock peri-
ods is 18. Of the 18 clock periods, 12 are used for the three read cycles (four periods per
cycle). Four additional clock periods are used for the single write cycle, for a total of 16 clock
periods. The bus is idle for two clock periods during which the processor completes the inter-
nal operations required for the instruction.
NOTE
The total number of clock periods (n) includes instruction fetch
and all applicable operand fetches and stores.
6.1 OPERAND EFFECTIVE ADDRESS CALCULATION TIMES
Table 6-1 lists the numbers of clock periods required to compute the effective addresses for
instructions. The totals include fetching any extension words, computing the address, and
fetching the memory operand. The total number of clock periods, the number of read cycles,
and the number of write cycles (zero for all effective address calculations) are shown in the
previously described format.
1. The SCM68000 is the name of the Verilog model for the EC000 core. The remainder of this section will refer
to the part as only the SCM68000.
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