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參數(shù)資料
| 型號(hào)： | EC000UM |
| 英文描述： | EC000 Core User＇s Manual (SCM68000) |
| 中文描述： | EC000核心用戶手冊（SCM68000） |
| 文件頁數(shù)： | 95/145頁 |
| 文件大?。?/td> | 829K |
| 代理商： | EC000UM |
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Bus Operation
3-12
EC000 CORE PROCESSOR USER’S MANUAL
MOTOROLA
STATE 2
On the rising edge of state 2 (S2), the SCM68000 asserts ASB and drives RWB to a logic
low.
STATE 3
During state 3 (S3), the data bus is driven out of the high-impedance state as data is
placed on the bus.
STATE 4
At the rising edge of state 4 (S4), the SCM68000 asserts DSB, and UDSB and/or LDSB.
The SCM68000 waits for a cycle termination signal (DTACKB or BERRB). If neither ter-
mination signal is asserted before the falling edge at the end of S4, the SCM68000 inserts
wait states (full clock cycles) until either DTACKB or BERRB is asserted. See 3.7 The Re-
lationship of DTACKB, BERRB, and HALTIB for a description of how DTACKB and
BERRB interact.
CASE 1: DTACKB is received alone or with BERRB (see 3.4 Bus Error and Halt Opera-
STATE 5
During state 5 (S5), no bus signals are altered.
STATE 6
During state 6 (S6), no bus signals are altered.
STATE 7
On the falling edge of the clock entering state 7 (S7), the SCM68000 negates ASB, UDSB,
LDSB, and DSB. As the clock rises at the end of S7, the SCM68000 places the data bus
in the high-impedance state and drives RWB and ERWB to a logic high. The device ne-
gates DTACKB or BERRB at this time.
CASE 2: BERRB is received without DTACKB (see 3.4 Bus Error and Halt Operation).
STATE 5
During state 5 (S5), no bus signals are altered.
STATE 6
During state 6 (S6), no bus signals are altered.
STATE 7
During state 7 (S7), no bus signals are altered.
STATE 8
During state 8 (S8), no bus signals are altered.
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Go to: www.freescale.com
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