參數(shù)資料
型號： EC000UM
英文描述： EC000 Core User＇s Manual (SCM68000)
中文描述： EC000核心用戶手冊（SCM68000）
文件頁數(shù)： 16/145頁
文件大?。?/td> 829K
代理商： EC000UM
8-Bit Instruction Execution Times
MOTOROLA
EC000 CORE PROCESSOR USER’S MANUAL
5-3
5.3 STANDARD INSTRUCTION EXECUTION TIMES
The numbers of clock periods listed in Table 5-5 indicate the times required to perform the
operations, store the results, and read the next instruction. The total number of clock peri-
ods, the number of read cycles, and the number of write cycles are shown in the previously
described format. The number of clock periods, the number of read cycles, and the number
of write cycles, respectively, must be added to those of the effective address calculation
where indicated by a plus sign (+).
In Table 5-5, the following notation applies:
An — Address register operand
Dn — Data register operand
ea — An operand specified by an effective address
M — Memory effective address operand
Table 5-3. Move Word Instruction Execution Times
Source
Destination
Dn
An
(An)
(An)+
–(An)
(d16, An)
(d8, An, Xn)*
(xxx).W
(xxx).L
Dn
An
(An)
8(2/0)
16(4/0)
8(2/0)
16(4/0)
16(2/2)
24(4/2)
16(2/2)
24(4/2)
16(2/2)
24(4/2)
32(6/2)
26(4/2)
34(6/2)
24(4/2)
32(6/2)
40(8/2)
(An)+
–(An)
(d16, An)
16(4/0)
18(4/0)
24(6/0)
16(4/0)
18(4/0)
24(6/0)
24(4/2)
26(4/2)
32(6/2)
24(4/2)
26(4/2)
32(6/2)
24(4/2)
26(4/2)
32(6/2)
34(6/2)
40(8/2)
34(6/2)
32(6/2)
42(8/2)
32(6/2)
34(6/2)
40(8/2)
42(8/2)
48(10/2)
(d8, An, Xn)*
(xxx).W
(xxx).L
26(6/0)
24(6/0)
32(8/0)
26(6/0)
24(6/0)
32(8/0)
34(6/2)
32(6/2)
40(8/2)
34(6/2)
32(6/2)
40(8/2)
34(6/2)
32(6/2)
40(8/2)
42(8/2)
40(8/2)
48(10/2)
44(8/2)
42(8/2)
50(10/2)
42(8/2)
40(8/2)
48(10/2)
50(10/2)
48(10/2)
56(12/2)
(d16, PC)
(d8, PC, Xn)*
#<data>
24(6/0)
26(6/0)
16(4/0)
24(6/0)
26(6/0)
16(4/0)
32(6/2)
34(6/2)
24(4/2)
32(6/2)
34(6/2)
24(4/2)
32(6/2)
34(6/2)
24(4/2)
40(8/2)
42(8/2)
32(6/2)
42(8/2)
44(8/2)
34(6/2)
40(8/2)
42(8/2)
32(6/2)
48(10/2)
50(10/2)
40(8/2)
*The size of the index register (Xn) does not affect execution time.
Table 5-4. Move Long Instruction Execution Times
Source
Destination
Dn
An
(An)
(An)+
–(An)
(d16, An)
(d8, An, Xn)*
(xxx).W
(xxx).L
Dn
An
(An)
8(2/0)
24(6/0)
8(2/0)
24(6/0)
24(2/4)
40(6/4)
24(2/4)
40(6/4)
24(2/4)
40(6/4)
32(4/4)
48(8/4)
34(4/4)
50(8/4)
32(4/4)
48(8/4)
40(6/4)
56(10/4)
(An)+
–(An)
(d16, An)
24(6/0)
26(6/0)
32(8/0)
24(6/0)
26(6/0)
32(8/0)
40(6/4)
42(6/4)
48(8/4)
40(6/4)
42(6/4)
48(8/4)
40(6/4)
42(6/4)
48(8/4)
50(8/4)
56(10/4)
50(8/4)
52(8/4)
58(10/4)
48(8/4)
50(8/4)
56(10/4)
58(10/4)
64(12/4)
(d8, An, Xn)*
(xxx).W
(xxx).L
34(8/0)
32(8/0)
40(10/0)
34(8/0)
32(8/0)
40(10/0)
50(8/4)
48(8/4)
56(10/4)
50(8/4)
48(8/4)
56(10/4)
50(8/4)
48(8/4)
56(10/4)
58(10/4)
56(10/4)
64(12/4)
60(10/4)
58(10/4)
66(12/4)
58(10/4)
56(10/4)
64(12/4)
66(12/4)
64(12/4)
72(14/4)
(d16, PC)
(d8, PC, Xn)*
#<data>
32(8/0)
34(8/0)
24(6/0)
32(8/0)
34(8/0)
24(6/0)
48(8/4)
50(8/4)
40(6/4)
48(8/4)
50(8/4)
40(6/4)
48(8/4)
50(8/4)
40(6/4)
56(10/4)
58(10/4)
48(8/4)
58(10/4)
60(10/4)
50(8/4)
56(10/4)
58(10/4)
48(8/4)
64(12/4)
66(12/4)
56(10/4)
*The size of the index register (Xn) does not affect execution time.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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