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參數(shù)資料
| 型號： | EC000UM |
| 英文描述： | EC000 Core User＇s Manual (SCM68000) |
| 中文描述： | EC000核心用戶手冊（SCM68000） |
| 文件頁數(shù)： | 84/145頁 |
| 文件大?。?/td> | 829K |
| 代理商： | EC000UM |
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Bus Operation
3-2
EC000 CORE PROCESSOR USER’S MANUAL
MOTOROLA
During operation in the 16-bit mode, byte operations can occur on either D15–D8 or D7–D0,
depending on A0. If A0 is zero, the upper byte is used and UDSB is asserted. If A0 is one,
the lower byte is used and LDSB is asserted. For word and long-word operations, A0 is
always zero, data bits D15 through D0 are used, and both LDSB and UDSB are asserted.
For long-word operations, data is transferred in two bus cycles with A1 indicating which half
of the long word is being transferred. The actual order of the long-word halves is instruction
and address-mode dependent.
The following paragraphs describe the read cycle, write cycle, read-modify-write cycle, and
CPU space cycle. The indivisible read-modify-write cycle allows interlocked multiprocessor
communications. A CPU space cycle is a special cycle used for interrupt acknowledge
cycles.
3.1.1 Read Cycle
During a read cycle, the SCM68000 receives data from memory or from a peripheral device.
When data is received, the SCM68000 correctly positions the byte internally.
The word read cycle flowchart is shown in Figure 3-1. The byte read cycle flowcharts for the
8-bit and 16-bit modes are shown in Figure 3-2 and Figure 3-3, respectively. The read cycle
and write cycle timing diagrams are shown in Figure 3-4 and Figure 3-5. The word and byte
read cycle timing diagram for operation in the 16-bit mode is shown in Figure 3-6.
Figure 3-1. Word Read Cycle Flowchart for 16-Bit Mode
BUS MASTER
ADDRESS THE DEVICE
1) SET RWB AND ERWB TO READ
2) PLACE FUNCTION CODE ON FC2–FC0
3) PLACE ADDRESS ON A31–A0
4) ASSERT ADDRESS STROBE (ASB)
5) ASSERT UPPER DATA STROBE
(UDSB), LOWER DATA STROBE (LDSB),
AND DATA STROBE (DSB)
ACQUIRE THE DATA
1) LATCH DATA
2) NEGATE UDSB, LDSB, AND DSB
3) NEGATE ASB
TERMINATE THE CYCLE
OUTPUT THE DATA
1) DECODE ADDRESS
2) PLACE DATA ON D15–D0
3) ASSERT DATA TRANSFER
ACKNOWLEDGE (DTACKB)
1) REMOVE DATA FROM D15–D0
2) NEGATE DTACKB
SLAVE
START NEXT CYCLE
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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