參數(shù)資料
型號(hào)： EC000UM
英文描述： EC000 Core User＇s Manual (SCM68000)
中文描述： EC000核心用戶手冊（SCM68000）
文件頁數(shù)： 66/145頁
文件大?。?/td> 829K
代理商： EC000UM
Overview
1-14
EC000 CORE PROCESSOR USER’S MANUAL
MOTOROLA
Register Codes
C
Carry Bit in CCR
cc
Condition Codes from CCR
N
Negative Bit in CCR
U
Undefined, Reserved for Motorola Use
V
Overflow Bit in CCR
X
Extend Bit in CCR
Z
Zero Bit in CCR
Stack Pointers
SP
Active Stack Pointer
SSP
Supervisor (Master or Interrupt) Stack Pointer
USP
User Stack Pointer
Miscellaneous
Effective Address
<label>
Assembly Program Label
<list>
List of registers, for example D3–D0.
Table 1-3. Instruction Set Summary
Opcode
Operation
Syntax
ABCD
Source10 + Destination10 + X → Destination
ABCD Dy,Dx
ABCD –(Ay), –(Ax)
ADD
Source + Destination
→ Destination
ADD <ea>,Dn
ADD Dn,<ea>
ADDA
Source + Destination
→ Destination
ADDA <ea>,An
ADDI
Immediate Data + Destination
→ Destination
ADDI # <data>,<ea>
ADDQ
Immediate Data + Destination
→ Destination
ADDQ # <data>,<ea>
ADDX
Source + Destination + X
→ Destination
ADDX Dy, Dx
ADDX –(Ay), –(Ax)
AND
Source
Λ Destination → Destination
AND <ea>,Dn
AND Dn,<ea>
ANDI
Immediate Data
Λ Destination → Destination
ANDI # <data>, <ea>
ANDI to CCR Source
Λ CCR → CCR
ANDI # <data>, CCR
ANDI to SR
If supervisor state
then Source
Λ SR → SR
else TRAP to Privilege Violation Trap
ANDI # <data>, SR
ASL, ASR
Destination Shifted by <count>
→ Destination
ASd Dx,Dy
ASd # <data>,Dy
ASd <ea>
Bcc
If (condition true) then PC + dn → PC
Bcc <label>
BCHG
~ (<bit number> of Destination)
→ Z;
~ (<bit number> of Destination)
→ <bit number> of Destination
BCHG Dn,<ea>
BCHG # <data>,<ea>
BCLR
~ (<bit number> of Destination)
→ Z;
0
→ <bit number> of Destination
BCLR Dn,<ea>
BCLR # <data>,<ea>
BKPT
Run breakpoint acknowledge cycle;
TRAP as illegal instruction
BKPT # <data>
BRA
PC + dn → PC
BRA <label>
BSET
~ (<bit number> of Destination)
→ Z;
1
→ <bit number> of Destination
BSET Dn,<ea>
BSET # <data>,<ea>
BSR
SP – 4
→ SP; PC → (SP); PC + dn → PC
BSR <label>
BTST
~ (<bit number> of Destination)
→ Z;
BTST Dn,<ea>
BTST # <data>,<ea>
CHK
If Dn < 0 or Dn > Source then TRAP to CHK Instruction Vector CHK <ea>,Dn
CLR
0
→ Destination
CLR <ea>
CMP
Destination – Source
→ cc
CMP <ea>,Dn
Table 1-2. Notational Conventions (Continued)
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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