參數(shù)資料
型號(hào)： celeron cpu Mobile Module
廠商： Intel Corp.
英文描述： processor Mobile Module Connector 1 (MMC-1) at 466 MHz and 433MHZ(工作頻率466和433兆赫茲帶連接器1處理器)
中文描述： 移動(dòng)處理器模塊連接器1（MMC管理- 1）在466 MHz和433MHz的（工作頻率466和433兆赫茲帶連接器1處理器）
文件頁(yè)數(shù)： 9/42頁(yè)
文件大?。?/td> 448K
代理商： CELERON CPU MOBILE MODULE
5
Celeron
Processor Mobile Module MMC-1
at 466 MHz and 433 MHz
3.1.2
Memory (108 Signals)
Table 2 lists the memory interface signals.
Table 2. Memory Signal Descriptions
Name
Type
Voltage
Description
MECC[7:0]
I/O
CMOS
O
CMOS
V_3
Memory ECC Data:
These signals carry Memory ECC data during access to DRAM.
These pins are not implemented on the MMC-1 connector.
RASA[5:0]# or
CSA[5:0]#
V_3
Row Address Strobe (EDO):
These pins select the DRAM row.
Chip Select (SDRAM):
These pins activate the SDRAMs.
SDRAM accepts any
command when its CS# pin is active low.
CASA[7:0]# or
DQMA[7:0]
O
CMOS
V_3
Column Address Strobe (EDO):
These pins select the DRAM column.
Input/Output Data Mask (SDRAM):
These pins act as synchronized output enables
during a read cycle and as a byte mask during a write cycle.
MAB[9:0]#
MAB[10]
MAB[12:11]#
MAB[13]
O
CMOS
V_3
Memory Address (EDO/SDRAM):
This is the row and column address for DRAM.
The
82443DX Host Bridge system controller has two identical sets of address lines (MAA
and MAB#). The Celeron processor mobile module MMC-1 supports only the MAB set of
address lines. For additional addressing features, please refer to the
Intel
a
440DX
PCIset Datasheet
.
MWE[A, B]#
O
CMOS
O
CMOS
V_3
Memory Write Enable (EDO/SDRAM):
MWEA# should be used as the write enable for
the memory data bus.
SRAS[A, B]#
V_3
SDRAM Row Address Strobe (SDRAM):
When active low, this signal latches Row
Address on the positive edge of the clock. This signal also allows Row access and pre-
charge.
SCAS[A, B]#
O
CMOS
V_3
SDRAM Column Address Strobe (SDRAM):
When active low, this signal latches
Column Address on the positive edge of the clock.
This signal also allows Column
access.
CKE[A, B]
O
CMOS
I/O
V_3
SDRAM Clock Enable (SDRAM):
When these signals are deasserted, SDRAM enters
power-down mode. CKEB is NC and not used by the system electronics.
MD[63:0]
CMOS
V_3
Memory Data:
These signals are connected to the DRAM data bus. They are not
terminated on the Celeron processor mobile module MMC-1.
相關(guān)PDF資料
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